ATTINY20-XU Atmel, ATTINY20-XU Datasheet - Page 145

• Manufacturer Part Number: ATTINY20-XU
• Description: MCU AVR 2KB FLASH 12MHZ 14TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-XU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, TWI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.4.1
17.4.1.1
8235B–AVR–04/11
Receiving Address Packets
Case 1: Address packet accepted - Direction bit set
TWI interrupt, or be used for polled operation. There are dedicated status flags for indicating
ACK/NACK received, clock hold, collision, bus error and read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond
or handle any data, and will in most cases require software interaction.
TWI slave operation. The diamond shapes symbols (SW) indicate where software interaction is
required.
Figure 17-11. TWI Slave Operation
The number of interrupts generated is kept at a minimum by automatic handling of most condi-
tions. Quick Command can be enabled to auto trigger operations and reduce software
complexity.
Promiscuous Mode can be enabled to allow the slave to respond to all received addresses.
When the TWI slave is properly configured, it will wait for a START condition to be detected.
When this happens, the successive address byte will be received and checked by the address
match logic, and the slave will ACK the correct address. If the received address is not a match,
the slave will not acknowledge the address and wait for a new START condition.
The slave Address/Stop Interrupt Flag is set when a START condition succeeded by a valid
address packet is detected. A general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition, is an illegal operation and the
Bus Error flag is set.
The R/W Direction flag reflects the direction bit received with the address. This can be read by
software to determine the type of operation currently in progress.
Depending on the R/W direction bit and bus condition one of four distinct cases (1 to 4) arises
following the address packet. The different cases must be handled in software.
If the R/W Direction flag is set, this indicates a master read operation. The SCL line is forced
low, stretching the bus clock. If ACK is sent by the slave, the slave hardware will set the Data
Interrupt Flag indicating data is needed for transmit. If NACK is sent by the slave, the slave will
wait for a new START condition and address match.
Figure
17-11. shows the
ATtiny20
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