MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 957

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

SRESET
SRESET
23.6.4
This register enables selectively masking the events that may cause the processor to enter into debug mode.
Freescale Semiconductor
Field
Field
Addr
22:27
Bits
28
29
30
31
MSB
—
16
—
0
0
RSTE CHSTPE
SEEE
Debug Enable Register (DER)
17
0
1
Name
EBRK
LBRK
IBRK
DPI
—
Bits
18
—
0:1
1
2
1
2
3
Reserved
L-bus breakpoint exception bit. This bit is set as a result of the assertion of a load/store
breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable
bit is set.
I-bus breakpoint exception bit. This bit is set as a result of the assertion of an Instruction
breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable
bit is set.
External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip
IMB or L-bus module, or by an external device or development system through the development
port). This bit is set as a result of the assertion of an external breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
Development port interrupt bit. Set by the development port as a result of a debug station
non-maskable request or when debug mode is entered immediately out of reset.
ITLBERE
MCEE
CHSTPE
19
3
0
MCEE
Name
RSTE
—
Table 23-18. ECR Bit Descriptions (continued)
Figure 23-17. Debug Enable Register (DER)
MPC561/MPC563 Reference Manual, Rev. 1.2
20
—
4
Table 23-19. DER Bit Descriptions
Reserved
Reset enable
0 Debug entry is disabled (reset value)
1 Debug entry is enabled
Checkstop enable bit
0 Debug mode entry disabled
1 Debug mode entry enabled (reset value)
Machine check exception enable bit
0 Debug mode entry disabled (reset value)
1 Debug mode entry enabled
0000_0000_0000
DTLBERE
—
21
5
EXTIE ALEE PREE FPUVEE DECEE
22
6
SPR 149
23
7
0000_0000_0
Description
Description
24
8
—
25
9
10
26
11
27
—
LBRKE IBRKE EBRKE DPIE
12
28
1
Development Support
SYSEE
13
29
0
1
TRE
14
30
1
1
23-43
FPASE
LSB
15
31
0
1