MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1058

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

IEEE 1149.1-Compliant Interface (JTAG)
25.1.2.1
The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is
a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in
Figure
rising edge of the TCK signal.
25.1.2.2
The MPC561/MPC563 scan chain implementation has a 427-bit (MPC563) or 423-bit (MPC561)
boundary scan register. This register contains bits for most device signals, clock pins and associated
control signals. The XTAL, EXTAL and XFC pins are associated with analog signals and are not included
in the boundary scan register. The PORESET, HRESET, and SRESET pins are also excluded from the
boundary scan register.
25-4
25-4. The value shown adjacent to each arc represents the value of the TMS signal sampled on the
TAP Controller
Boundary Scan Register
1
0
RUN-TEST/IDLE
TEST LOGIC
RESET
0
Figure 25-4. TAP Controller State Machine
MPC561/MPC563 Reference Manual, Rev. 1.2
1
1
0
1
SELECT-DR_SCAN
CAPTURE-DR
UPDATE-DR
PAUSE-DR
SHIFT-DR
EXIT1-DR
EXIT2-DR
0
0
1
0
1
1
0
0
0
0
1
1
0
1
SELECT-IR_SCAN
CAPTURE-IR
UPDATE-IR
PAUSE-IR
SHIFT-IR
EXIT1-IR
EXIT2-IR
0
0
1
0
1
1
0
0
0
Freescale Semiconductor
1
1