MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 292

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Reset
7.3
The MPC561/MPC563 supports data coherency and avoids data corruption during reset. If a cycle is
executing when any SRESET or HRESET source is detected, then the cycle will either complete or will
not start before generating the corresponding reset control signal. There are reset sources, however, when
the MPC561/MPC563 generates an internal reset due to special internal situations where this protection is
not supported. See
In the case of large operand size (32 or 16 bits) transactions to a smaller port size, the cycle is split into
two 16-bit or four 8-bit cycles. In this case, data coherency is assured and data will not be corrupted.
In the case where the core executes an unaligned load/store cycle which is broken down into multiple
cycles, data coherency is NOT assured between these cycles (i.e., data could be corrupted).
Contention may occur if a write access is in progress to external memory and SRESET/HRESET is
asserted and the external reset configuration word (RCW) is used. In this case, the external RCW drivers,
usually activated by HRESET/SRESET lines, will drive the data bus together with the MPC561/MPC563.
Thus the data in the RAM may be corrupted regardless of the data coherency mechanism in the
MPC561/MPC563.
7-4
HRESET
Power-On Reset
(PORESET)
Hard Reset (HRESET)
Sources:
Soft Reset (SRESET)
Sources:
• External Hard Reset
• Loss of Lock
• On-Chip Clock Switch
• Illegal Low-Power Mode
• Software Watchdog
• Checkstop
• Debug Port Hard Reset
• External Soft Reset
• Debug Port Soft Reset
• JTAG Reset
Data Coherency During Reset
Reset Source
Reset Driven
Table 7-2. Reset Configuration Word and Data Corruption/Coherency
Section 7.4, “Reset Status Register
Table 7-1. Reset Action Taken for Each Reset Cause
Logic and
States
Reset
Reset
PLL
MPC561/MPC563 Reference Manual, Rev. 1.2
Yes
No
No
SRESET
Coherency (EXT_RESET)
Reset to Use for Data
Configuratio
n Reset
System
Yes
Yes
No
Module
Clock
Reset
(RSR).”
Yes
Yes
No
HRESET
Driven
Yes
Yes
Pin
No
Configuratio
Debug Port
Yes
Yes
Yes
n
Comments
Freescale Semiconductor
Internal
Reset
Other
Logic
Yes
Yes
Yes
SRESET
Driven
Pin
Yes
Yes
Yes

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