MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 843

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

19.4.3
This register is accessible only when the TPU is in test mode; see
Registers.”
Freescale Semiconductor
1
T4 is one of the four basic timers (T1, T2, T3 & T4) used for microengine timing.
Bits
7:8
10
11
12
13
14
15
9
Development Support Status Register (DSSR)
Name
CCL
FRZ
BM
BP
BC
BH
BL
BT
FREEZE assertion response. The FRZ bits specify the TPU microengine response to the IMB3
FREEZE signal
00 Ignore freeze
01 Reserved
10 Freeze at end of current microcycle
11 Freeze at next time-slot boundary
Channel Conditions Latch. CCL controls the latching of channel conditions match recognition
latch (MRL) and transition detect latch (TDL) when the CHAN register is written. Refer to the TPU
Reference Manual (TPURM/AD) for further information.
0 Only the pin state condition of the new channel is latched as a result of the write CHAN register
1 Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write CHAN
Breakpoint enable for microprogram counter (µPC)
0 Breakpoint not enabled
1 Break if µPC equals µPC breakpoint register
Channel breakpoint enable
0 Breakpoint not enabled
1 Break if CHAN register equals channel breakpoint register at beginning of state or when
Host service breakpoint enable
0 Breakpoint not enabled
1 Break if host service latch is asserted at beginning of state
Link service breakpoint enable
0 Breakpoint not enabled
1 Break if link service latch is asserted at beginning of state
MRL breakpoint enable
0 Breakpoint not enabled
1 Break if MRL is asserted at beginning of state
TDL breakpoint enable
0 Breakpoint not enabled
1 Break if TDL is asserted at beginning of state
microinstruction
register microinstruction
CHAN is changed through microcode
Table 19-8. DSCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Section 19.4.14, “Factory Test
Time Processor Unit 3
19-13