MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 639
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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15.6.1.5
The SPSR contains information concerning the current serial transmission. Only the QSPI can set bits in
this register. To clear status flags, the CPU reads SPSR with the flags set and then writes the SPSR with
zeros in the appropriate bits. Writes to CPTQP have no effect.
Freescale Semiconductor
Note: See bit descriptions in
SRESET
1
2
See bit descriptions in
SPSR can be accessed as an 8-bit register at location 0x30 501F or 0x30 541F.
Bits
8:15
SRESET
0:4
5
6
7
Field
Addr
Field
Addr
MSB
LOOPQ
QSPI Status Register (SPSR)
0
Name
SPSR
HMIE
HALT
MSB
—
0
1
1
Reserved
QSPI loop mode. LOOPQ controls feedback on the data serializer for testing.
0 Feedback path disabled.
1 Feedback path enabled.
HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA
status flag or the MODF status flag in SPSR.
0 HALTA and MODF interrupts disabled.
1 HALTA and MODF interrupts enabled.
from which it can later be restarted. Refer to
the
0 QSPI operates normally.
1 QSPI is halted for subsequent restart.
Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
See
—
Table 15-17
2
SPI.”
2
Table 15-18
Table 15-18
3
Figure 15-14. SPCR3 — QSPI Control Register 3
SPCR3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 15-15. QSPI Status Register (SPSR)
Table 15-17. SPCR3 Bit Descriptions
4
4
1
for bit descriptions.
LOOPQ HMIE HALT
5
5
6
0000_0000_0000_0000
0000_0000_0000_0000
6
0x30 501E (SPSR)
7
0x30 501E
7
SPIF MODF HALTA
Description
8
Section 15.6.4.1, “Enabling, Disabling, and Halting
8
9
2
9
10
10
11
Queued Serial Multi-Channel Module
11
SPSR*
12
12
CPTQP
13
13
14
14
LSB
15
LSB
15
15-21
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