MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 295

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

7.5
7.5.1
When a hard reset event occurs, the MPC561/MPC563 reconfigures its hardware system as well as the
development port configuration. The logical value of the bits that determine its initial mode of operation,
are sampled from the following:
If at the sampling time RSTCONF is asserted, then the configuration is sampled from the external data
bus. If RSTCONF is negated and a valid NVM value exists (UC3FCFIG[HC]=0), then the configuration
is sampled from the NVM register in the UC3F module. If RSTCONF is negated and no valid NVM value
exists (UC3FCFIG[HC]=1), then the configuration word is sampled from the internal default (all zeros).
HC will be “1” if the internal Flash is erased.
If the PRDS control bit in the PDMCR register is cleared and HRESET and RSTCONF are asserted, the
MPC561/MPC563 pulls the data bus low with a weak resistor. The user can overwrite this default by
driving the appropriate bit high. See
Freescale Semiconductor
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•
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The external data bus pins DATA[0:31]
An internal default constant (0x0000 0000)
An internal NVM register value (UC3FCFIG). Available on the MPC563/MPC564 only.
Reset Configuration
RSTCONF
Hard Reset Configuration
0
1
1
Has Configuration (HC)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 7-4. Reset Configuration Options
x
0
1
Figure 7-2
Table 7-4
for the basic reset configuration scheme.
DATA[0:31] pins
NVM Flash EEPROM register (UC3FCFIG)
Internal data word default (0x0000 0000)
summarizes the reset configuration options.
Internal Configuration Word
Reset
7-7