MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 343

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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9.4
Table 9-1
subsequent subsections. The buses are described in big endian manner, which means that bit 0 is the most
significant bit in a bus (MSB), and bit 31 is the least significant bit (LSB).
Freescale Semiconductor
Bus Interface Signal Descriptions
describes each signal in the bus interface unit. More detailed descriptions can be found in
Interface
Bus
Figure 9-2. MPC561/MPC563 Bus Signals
MPC561/MPC563 Reference Manual, Rev. 1.2
24
32
1
1
2
4
1
1
1
1
1
1
1
1
1
1
1
1
1
RETRY
ADDR[8:31]
RD/WR
BURST
TSIZ[0:1]
AT[0:3]
PTR
BDIP
TS
RSV
KR
CR
DATA[0:31]
BI / STS
TA
TEA
BR
BG
BB
Reservation
Termination
Attributes
Address
Transfer
Transfer
Protocol
Transfer
Arbitration
Cycle
Data
Start
and
External Bus Interface
9-3

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