MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 728

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

CAN 2.0B Controller Module
16-34
10:11
Bits
0:1
12
2
3
4
5
6
7
8
9
STUFFERR
FORMERR
RXWARN
CRCERR
TXWARN
ACKERR
BITERR
TX/RX
Name
IDLE
FCS
—
Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
Refer to
NOTE: The transmit bit error field is not modified during the arbitration field or the ACK slot
bit time of a message, or by a transmitter that detects dominant bits while sending a passive
error frame.
Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been
correctly received for a transmitted message.
0 No ACK error was detected since the last read of this register
1 An ACK error was detected since the last read of this register
Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the
last transmitted or received message was valid.
0 No CRC error was detected since the last read of this register
1 A CRC error was detected since the last read of this register
Message format error. The FORMERR bit indicates whether or not the message format of
the last transmitted or received message was correct.
0 No format error was detected since the last read of this register
1 A format error was detected since the last read of this register
Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in
the last transmitted or received message was correct.
0 No bit stuffing error was detected since the last read of this register
1 A bit stuffing error was detected since the last read of this register
Transmit error status flag. The TXWARN status flag reflects the status of the TouCAN
transmit error counter.
0 Transmit error counter < 96
1 Transmit error counter ≥ 96
Receiver error status flag. The RXWARN status flag reflects the status of the TouCAN
receive error counter.
0 Receive error counter < 96
1 Receive error counter ≥ 96
Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 The CAN bus is not idle
1 The CAN bus is idle
Transmit/receive status. The TX/RX bit indicates when the TouCAN module is transmitting or
receiving a message. TX/RX has no meaning when IDLE = 1.
0 The TouCAN is receiving a message if IDLE = 0
1 The TouCAN is transmitting a message if IDLE = 0
Fault confinement state. The FCS[1:0] field describes the state of the TouCAN. Refer to
Table
If the SOFTRST bit in CANMCR is asserted while the TouCAN is in the bus off state, the error
and status register is reset, including FCS[1:0]. However, as soon as the TouCAN exits reset,
FCS[1:0] bits will again reflect the bus off state. Refer to
more information on entry into and exit from the various fault confinement states.
Reserved
16-25.
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-23. ESTAT Bit Descriptions
16-24.
Description
Section 16.3.4, “Error
Freescale Semiconductor
Counters” for