MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 541

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

The current into the signal (I
equations:
where:
The current into (I
parasitic bipolar transistor (K
where I
A method for minimizing the impact of stress conditions on the QADC64E is to strategically allocate
QADC64E inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress
conditions.
Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress
conditions.
Freescale Semiconductor
INJ
is either I
V
V
(refer to V
V
(refer to V
R
(10-kΩ resistor in
R
I
IN
STRESS
SELECTED
STRESS
EB
BE
= - K
IN
= Parasitic NPN base/emitter voltage
= Parasitic PNP emitter/base voltage
) the neighboring signal is determined by the K
INJN
= Source impedance
= Adjustable voltage source
N
NEGCLAMP
NEGCLAMP
or I
= Source impedance on channel selected for conversion
* I
Figure 13-55. Input Signal Subjected to Positive Stress
INJ
INJP
INJN
N
V
<< 1). The I
.
IN
or I
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 13-54
V
I INJP
in
in
STRESS
I INJN
INJP
Appendix F, “Electrical
Appendix F, “Electrical
+
) under negative or positive stress is determined by the following
=
=
V STRESS V EB
--------------------------------------------------------------------- -
–
----------------------------------------------------- -
IN
R
(
V STRESS V BE
SELECTED
R
can be expressed by the following equation:
and
STRESS
R STRESS
10K
R STRESS
Figure 13-55
–
I
INJP
I
–
IN
PARASITIC
–
DEVICE
AN
AN
V DDA
)
n+1
n
Characteristics”)
Characteristics”)
Signal Under
Adjacent
on stressed channel)
Stress
signal
N
(current coupling ratio) of the
V
DDA
QADC64E Legacy Mode Operation
QADC64E PAR
Eqn. 13-2
Eqn. 13-3
13-77