MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 35

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

A.2.1
A.2.2
A.2.3
A.2.4
A.2.5
A.2.6
A.2.7
A.2.8
A.2.8.1
A.2.8.2
A.2.8.3
A.2.9
A.2.9.1
A.2.9.2
A.2.9.3
A.2.9.4
A.2.9.5
A.2.10
A.2.11
A.2.12
A.2.13
A.2.14
A.2.14.1
A.2.14.2
A.3
A.3.1
A.3.1.1
A.3.1.2
A.3.1.2.1
A.3.2
A.3.3
A.3.3.1
A.4
Freescale Semiconductor
Paragraph
Number
Operation Modes........................................................................................................... A-14
Decompressor Class Configuration Registers (DCCR0-15) ........................................ A-18
Compression Model Features ..................................................................................... A-1
Model Limitations....................................................................................................... A-2
Instruction Class-Based Compression Algorithm....................................................... A-2
Compressed Address Generation with Direct Branches............................................. A-4
Compressed Address Generation—Indirect Branches ............................................... A-6
Compressed Address Generation—Exceptions .......................................................... A-6
Class Code Compression Algorithm Rules ................................................................ A-7
Bypass Field Compression Rules ............................................................................... A-7
Instruction Class Structures and Programming .......................................................... A-8
Instruction Layout Programming Summary ..............................................................A-11
Compression Process .................................................................................................A-11
Decompression.......................................................................................................... A-12
Compression Environment Initialization .................................................................. A-13
Compression/Non-Compression Mode Switch ........................................................ A-14
Instruction Fetch ....................................................................................................... A-14
Vocabulary Table Storage Operation ........................................................................ A-16
READI Compression ................................................................................................ A-16
Branch Right Segment Compression #1................................................................. A-7
Branch Right Segment Compression #2................................................................. A-8
Right Segment Zero Length Compression Bypass................................................. A-8
Global Bypass......................................................................................................... A-8
Single Segment Full Compression – CLASS_1 ..................................................... A-9
Twin Segment Full Compression – CLASS_2 ....................................................... A-9
Compression Definition for Exception Handlers ................................................. A-14
Running Mixed Code............................................................................................ A-14
Decompression Off Mode..................................................................................... A-15
Decompression On Mode ..................................................................................... A-15
I-Bus Support Control Register (ICTRL) ............................................................. A-16
Left Segment Compression and Right Segment Bypass – CLASS_3................. A-10
Left Segment Bypass and Right Segment Compression—CLASS_4..................A-11
Show Cycles in Decompression On Mode ....................................................... A-15
MPC561/MPC563 Reference Manual, Rev. 1.2
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