DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 49

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Simulation/Verification
Synthesis Tab (Schematic Flow)
Logic Simulator
Timing Analyzer
•
In a Schematic Flow project, the necessary synthesis of any under-
lying HDL macros in the design can be initiated in the various design
entry tools.The Synthesis tab provides the capability to synthesize
any or all of the HDL macros (FSM, ABEL, VHDL, or Verilog) in the
current project and update the macro symbol and netlist without
searching manually through the project and synthesizing/updating
them individually.
Simulation and verification tools are available for both Schematic and
HDL Flow projects to determine if the timing requirements and func-
tionality of your design have been met.
The Logic Simulator is a real-time interactive design tool for both
functional and timing simulation of designs. You access the Logic
Simulator from the project flowchart when you click the Simula-
tion button or the Timing Simulation icon on the Verification
button.
The Logic Simulator creates an electronic breadboard of your design
directly from your design’s netlist. The breadboard is tested with
signals called test vectors. Each test vector lists logical states of all
stimulus signals at a selected time interval. See the “Functional Simu-
lation” chapter and the “Verification and Programming” chapter for
more information on simulations. For details on how to use the Logic
Simulator, select Help
Simulator.
Select the Timing Analyzer icon on the Verification button on the
project flowchart to access the Timing Analyzer for verification based
on the post-layout timing netlist. The Timing Analyzer is used to
verify that the delay along a given path or paths meets your specified
Graphical constraints editor. The Express Constraints Editor GUI
is available to Foundation Express users only. It is used to set
design constraints and view estimated design performance.
Foundation Help Contents
Project Toolset
Logic
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