DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 283

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
The Offset Constraint
Furthermore, the example shows how constraints and nets may be
given the same name because they occupy separate name-spaces.
Also, it shows the constraint syntax whereby one Timespec is defined
relative to another (the value of TS04 is declared to be two times that
of TS03).
The PERIOD constraint covers all timing paths which start or end at a
register, latch, or synchronous RAM that is clocked by the referenced
net. The only exception to this rule are paths to output pads, which
are not covered by the PERIOD constraint. (Input pads, which are the
source of a “pad-to-setup” timing path for one of the specified
synchronous elements, are covered by the PERIOD constraint.)
The flexibility of the TIMESPEC form of the PERIOD constraint arises
from being able to modify the contents of the TIMEGRP once the
design has been mapped. By adding or removing objects from the
TIMEGRP, which are listed in the PCF file, you can alter the paths
that are covered by the PERIOD constraint.
If you do not need the flexibility offered by the TIMESPEC form, you
can use the NET form of the PERIOD constraint may be used. The
syntax for the NET form of the PERIOD constraint is simpler than the
TIMESPEC form, while continuing to provide the same path
coverage. The following example illustrates the syntax of the NET
form of the PERIOD constraint.
This is the recommendation of using PERIOD on a single clock design
in which data does not pass between the clock domains.
With the Foundation 1.5 release, PERIOD will now include clock
skew in the path analysis.
Use offsets to define the timing relationship between an external
clock and its associated data-in or data-out-pin. Using this option,
you can do the following.
# NET form of the PERIOD timing constraint
# (no TSidentifier)
TIMESPEC TS03 = PERIOD CLK2_GRP 50 ;
TIMESPEC TS04 = PERIOD CLK3 TS03 * 2 ;
NET CLK PERIOD = 40 ;
Foundation Constraints
B-11