DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 173

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

HDL Design Entry and Synthesis
Each primitive in a LogiBLOX RAM/ROM module has an instance
name of MEMx_y, where y represents the primitive position in the
bank of memory, and where x represents the bit position of the RAM/
ROM output.
Referencing LogiBLOX Entities
This section is written in terms of the Verilog example, using the files
illustrated in Figures 6-6 through 6-9. This section also applies to the
VHDL example in Figures 6-10 through 6-13.
LogiBLOX RAM/ROM modules in an HDL Flow project are
constrained using a UCF file.
LogiBLOX RAM/ROM modules instantiated in the HDL code can be
referenced by the complete hierarchical instance name. If a LogiBLOX
RAM/ROM module is at the top-level of the HDL code, then the
instance name of the LogiBLOX RAM/ROM module is just the
instantiated instance name. In the case of a LogiBLOX RAM/ROM
that is instantiated within the hierarchy of the design, the instance
name of the LogiBLOX RAM/ROM module is the full hierarchical
path to the LogiBLOX RAM/ROM. The hierarchy level names are
listed from the top level down and are separated by a "_".
In the Verilog example, the RAM32X1S is named "memory". The
memory module is instantiated in the Verilog module "inside" with
an instance name "U1". "inside" is instantiated in the top-level
module "test" with an instance name "U0". Therefore, the RAM32X1S
can be referenced in a UCF file as "U0_U1". For example, to attach a
TNM to this block of RAM, the following line could be used in the
UCF file:
INST “U0_U1” TNM=block1;
Since U0_U1 is composed of two RAM primitives, a timegroup called
block1 is created; the block1 TNM can be used throughout the UCF
file as a timespec end/start point, and/or U0_U1 could have a LOC
area constraint applied to it. If the RAM32X1S has been instantiated
in the top-level file and the instance name used in the instantiation is
U1, then this block of RAM can just be referenced by U1.
Sometimes it is necessary to apply constraints to the primitives that
compose the LogiBLOX RAM/ROM module. For example, if you
choose a floorplanning strategy to implement your design, it may be
necessary to apply LOC constraints to one or more primitives inside a
Foundation Series 2.1i User Guide
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