DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 126

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
HDL Designs with Instantiated Xilinx Unified Library
Components
5-24
It is possible to instantiate certain Xilinx Unified Library components
directly into your VHDL or Verilog code. In general, you will find this
most useful for components that the Express compiler is unable to
infer, such as BSCAN, RAM, and certain types of special Xilinx
components. The “Instantiated Components” appendix lists the most
commonly instantiated components, including descriptions of their
function and pins.
When instantiating Unified Library components, the component
must first be declared before the begin keyword in VHDL the archi-
tecture and then may be instantiated multiple times in the body of the
architecture.
The following example shows how to instantiate the STARTUP
component in a VHDL file, which in turn allows use of the dedicated
GSR (global set/reset) net.
The following sample written in VHDL shows an example of an
instantiated Xilinx Unified Library component, STARTUP.
library IEEE;
use IEEE.std_logic_1164.all;
For more information about creating state machine modules,
refer to the“State Machine Designs” chapter. Or, select Help
Foundation Help Contents and then Click State Editor.
entity gsr_test is
end gsr_test;
architecture gsr_test_arch of gsr_test is
component STARTUP
end component;
port (
);
port (GSR: in std_logic);
CLK: in STD_LOGIC;
D_IN: in STD_LOGIC;
RESET: in STD_LOGIC;
Q_OUT: out STD_LOGIC
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