DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 138

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
5-36
CORE Generator COREs in a VHDL or Verilog Design
8.
9.
Note: When the design is synthesized, a warning is generated that
the LogiBLOX module is unlinked. Modules instantiated as black
boxes are not elaborated and optimized. The warning message is just
reflecting the black box instantiation.
10. To complete the design, refer to the “Synthesizing the Design”
CORE Generator COREs may be generated in Foundation and then
instantiated in VHDL or Verilog code. COREs can be generated for
valid Foundation projects only.
This flow may be used for any CORE Generator CORE. The CORE
being instantiated must be located in the HDL project directory (that
is, the directory where the top-level HDL file resides). Running Logi-
BLOX from the Foundation project ensures this condition is met.
VHDL Instantiation
This section explains how to instantiate a CORE component into a
VHDL design using Foundation.
1.
//
//
//---------------------------------------------------
module MEMORY (A, DO, DI, WR_EN, WR_CLK);
input [5:0] A;
output [3:0] DO;
input [3:0] DI;
input WR_EN;
input WR_CLK;
endmodule
Check the syntax of the Verilog design code by selecting
Synthesis
errors and then save the design and close the HDL Editor.
The design with the instantiated LogiBLOX module can then be
synthesized (click the Synthesis button on the Flow tab).
section through the “Programming the Device” section under the
“All-HDL Designs” section in this chapter.
With a valid Foundation project open, access the CORE
Generator window using one of the following methods. Its
operation is the same regardless of where it is invoked.
STYLE = MAX_SPEED
USE_RPM = FALSE
Check Syntax in the HDL Editor. Correct any
Xilinx Development System