DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 163

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
HDL Flow Methodology
In an HDL Flow project, all top-level VHDL and Verilog files and
schematics are exported to the synthesis tool and optimized. Pre-
Implementation constraint editing, cross-boundary optimization, and
auto I/O buffer insertion are only available in an HDL Flow Project.
The HDL Flow approach provides an easier method of compilation. It
requires only a single synthesis action for all HDL modules. In
addition, this method includes optional cross-boundary optimization
of the entire design, editing of constraints prior to implementation,
and auto I/O buffer insertion.
Following is the general procedure to synthesize HDL modules in
HDL Flow Projects.
1.
2.
Be sure that all HDL files are added to the project. See the
“Adding the File to the Project” section for instructions on
adding files to a project. Underlying HDL macros in top-level
schematics in HDL projects are an exception to this; files for those
HDL macros are added automatically during synthesis.
From the Project Manager window, set the global synthesis
options by selecting Synthesis
Synthesis Options dialog box.
HDL Design Entry and Synthesis
Options to open the
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