DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 280

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
B-8
Using TPSYNC
Note: All From:To Timespecs must be relative to a Timegroup. The
above example illustrates that you can define Timegroups either
explicitly (TIMEGRPs) or implicitly (TNMs), or they may be
predefined groups (PADS, LATCHES, FFS, RAMS).
There is an additional keyword that you can add to the From:To spec-
ification that allows the user to narrow the set of paths that are
covered—THRU. By using the From:Thru:To form of a Timespec, you
are able to constrain only those paths that go through a certain set of
nets, defined by the TPTHRU keyword, as shown in the following
example.
Here, only those paths that go from the Q pin of the sflops through the
nets
will be controlled by TS23.
(FPGA only.) In the Foundation design implementation tools, you can
define any node as a source or destination for a Timespec with the
TPSYNC keyword. The use of TPSYNC is similar to TPTHRU—it is a
label that is attached to a set of nets, pins, or instances in the design.
For example, suppose a design has a PAD ENABLE_BUS that must
arrive at the enable pin of several different 3-state buffers in less than
a specified time. With the Foundation tools, you can now define that
3-state buffer as an endpoint for a timing spec. The following figure
illustrates TPSYNC.
# UCF example of FROM:TO Timespec using THRU
$1I6/thisnet
NET $1I6/thisnet TPTHRU=these ;
NET $1I6/thatnet TPTHRU=these ;
TIMEGRP sflops=FFS(DATA*) ;
TIMEGRP dflops=FFS(OUTREG*) ;
TIMESPEC TS23=FROM:sflops:THRU:these:TO:dflops:20 ;
and
$1I6/thatnet
and on to the D pin of dflops
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