DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 293

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Standard Block Delay Symbols
The “Timing Symbols and Their Default Values” table lists the block
delay symbols, each with their corresponding description. There is a
one-to-many correspondence between these symbol names and the
Programmable Logic Data Book symbol names. For those symbols listed
with a disabled default, no timing analysis is performed on paths that
have a segment composed of symbol path. For example, paths which
have a set/reset to output path will not be analyzed. Any of the block
delays (Symbol) listed in the table may be explicitly enabled or
disabled using the PCF file.
The following example shows the PCF syntax that enables the path
tracing for all paths that contain RAM data to out paths. This PCF
directive is placed in the user section of the PCF.
Table B-1 Timing Symbols and Their Default Values
reg_sr_q
lat_d_q
ram_d_o
ram_we_o
tbuf_t_o
tbuf_i_o
io_pad_I
io_t_pad
req_sr_clk
Symbol
TIMESPEC TS04 = FROM SPDRAM THRU RAMVIA TO FFS 45 ;
SCHEMATIC END;
// This is a PCF comment line
// Enable RAM data to out path tracing
ENABLE = ram_d_o;
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Default
Set/reset to output propagation delay
Data to output transparent latch delay
RAM data to output propagation delay
RAM write enable to output propaga-
tion delay
TBUF tristate to output propagation
delay
TBUF input to output propagation
delay
IO pad to input propagation delay
IO tristate to pad propagation delay
Set/Reset to clock setup and hold
checks
Description
Foundation Constraints
B-21