DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 122

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
5-20
Verifying the Design
After the design has been implemented, the Timing Analyzer or the
Timing Simulator can be used to verify the design. The Timing
Analyzer performs a static timing analysis of the design. The Timing
Simulator uses worst-case delays and user input stimulus to simulate
the design.
Performing a Static Timing Analysis
1.
2.
For details on how to use the Timing Analyzer, select Help
dation Help Contents
Performing a Timing Simulation
1.
2.
Click the Timing Analyzer icon in the Verification box on the
Project Manager’s Flow tab to perform a static timing analysis.
For FPGAs, you can perform a post-MAP, post-place, or post-
route timing analysis to obtain timing information at various
stages of the design implementation. You can perform a post-
implementation timing analysis on CPLDs after a design has
been fitted.
Open the Timing Simulator by clicking the Timing Simulation
icon in the Verification box on the Project Managers’s Flow tab.
The implementation timing netlist with worst-case delays will be
loaded into the simulator.
The Waveform Viewer window displays inside the Logic Simu-
lator window.
Refer to the “Performing Functional Simulation” section earlier
in this chapter for instructions on simulating the design. (The
Timing Analyzer.
Xilinx Development System
Foun-