DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 26

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Chapter 12 Verification and Programming
Appendix A Glossary
xvi
Flow Engine ................................................................................... 11-22
Implementation Reports ................................................................. 11-26
Additional Implementation Tools .................................................... 11-29
Overview ........................................................................................ 12-1
Timing Simulation........................................................................... 12-2
Timing Analyzer ............................................................................. 12-4
In-Circuit Verification ...................................................................... 12-7
Downloading a Design ................................................................... 12-7
ABEL .............................................................................................. A-1
Translate ................................................................................... 11-24
MAP (FPGAs) ........................................................................... 11-24
Place and Route (FPGAs) ........................................................ 11-24
CPLD Fitter ............................................................................... 11-25
Configure (FPGAs) ................................................................... 11-26
Bitstream (CPLDs) .................................................................... 11-26
Translation Report .................................................................... 11-28
Map Report (FPGAs) ................................................................ 11-28
Place and Route Report (FPGAs)............................................. 11-28
Pad Report (FPGAs)................................................................. 11-29
Fitting Report (CPLDs).............................................................. 11-29
Post Layout Timing Report ....................................................... 11-29
Constraints Editor ..................................................................... 11-29
Flow Engine Controls................................................................ 11-30
Floorplanner.............................................................................. 11-34
FPGA Editor.............................................................................. 11-35
CPLD ChipViewer ..................................................................... 11-35
Locking Device Pins.................................................................. 11-35
Generating a Timing-annotated Netlist ..................................... 12-3
Basic Timing Simulation Process.............................................. 12-3
Post Implementation Static Timing Analysis ............................. 12-5
Summary Timing Reports ......................................................... 12-5
Detailed Timing Analysis........................................................... 12-6
JTAG Programmer.................................................................... 12-8
Hardware Debugger (FPGAs only) ........................................... 12-9
PROM File Formatter................................................................ 12-9
Controlling Flow Engine Steps............................................. 11-30
Running Re-Entrant Routing on FPGAs .............................. 11-31
Configuring the Flow............................................................ 11-33
Xilinx Development System