DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 240

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
11-34
Floorplanner
button by mistake and want to reset the implementation state to its
original state.
5.
6.
The Floorplanner is a graphical placement tool that gives you control
over placing a design into a target FPGA. You can access the Floor-
planner through Tools
the Project Manager’s menu bar.
Floorplanning is an optional methodology to help you improve
performance and density of a fully, automatically placed and routed
design. Floorplanning is particularly useful on structured designs
and data path logic. With the Floorplanner, you see where to place
logic in the floorplan for optimal results, placing data paths exactly at
the desired location on the die.
With the Floorplanner, you can floorplan your design prior to or after
running PAR. In an iterative design flow, you floorplan and place and
route, interactively. You can modify the logic placement in the Floor-
plan window as often as necessary to achieve your design goals. You
can save the iterations of your floorplanned design to use later as a
constraints file for PAR.
The Floorplanner displays a hierarchical representation of the design
in the Design Hierarchy window using hierarchy structure lines and
colors to distinguish the different hierarchical levels. The Floorplan
window displays the floorplan of the target device into which you
place logic from the hierarchy. The following figure shows the
windows on the PC version.
Logic symbols represent each level of hierarchy in the Design Hier-
archy window. You can modify that hierarchy in the Floorplanner
without changing the original design.
You use the mouse to select the logic from the Design Hierarchy
window and place it in the FPGA represented in the Floorplan
window.
Select Use Flashing to Indicate Heartbeat to enable
flashing icons to indicate that a process step is being processed. A
trade-off of this feature is that flashing icons slow down the
implementation process.
Click OK.
Implementation
Xilinx Development System
Floorplanner on