DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 265

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
one-hot encoding
optimization
optimize
PAR (Place and Route)
path delay
PCF file
For state machines, in one-hot encoding, an individual state register
is dedicated to one state. Only one flip-flop is active, or hot, at any
one time.
Optimization is the process that decreases the area or increases the
speed of a design. Foundation allows you to control optimization of a
design on a module-by-module basis. This means that you have the
ability to, for instance, optimize certain modules of your design for
speed, some for area, and some for a balance of both.
The third step in the FPGA Express synthesis flow. In this stage, the
implemented design is re-synthesized with constraints the user speci-
fies. This is the final step before writing out the XNF file from FPGA
Express.
PAR is a program that takes an NCD file, places and routes the
design, and outputs an NCD file. The NCD file produced by PAR can
be used as a guide file for reiterative placement and routing. The
NCD file can also be used by the bitstream generator, BitGen.
A path delay is the time it takes for a signal to propagate through a
path.
The PCF file is an output file of the MAP program. It is an ASCII file
containing physical constraints created by the MAP program as well
as physical constraints entered by you. You can edit the PCF file from
within the FPGA Editor. (FPGA only)
Glossary
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