DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 150

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DS-FND-BSX-PC

Manufacturer Part Number
DS-FND-BSX-PC
Description
FOUNDATION BASE SYS W/SYN EXPRES
Manufacturer
Xilinx Inc
Type
Foundation Systemr
Datasheet

Specifications of DS-FND-BSX-PC

For Use With/related Products
Xilinx Programmable Logic Devices
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1185
Foundation Series 2.1i User Guide
5-48
XNF file in a VHDL or Verilog Design
12. Check the syntax of the VHDL design code by selecting
13. The design with the instantiated CORE module can then be
Note: When the design is synthesized, a warning is generated that
the CORE module is unexpanded. Modules instantiated as black
boxes are not elaborated and optimized. The warning message is just
reflecting the black box instantiation.
14. To complete the design, refer to the “Synthesizing the
Note: The instantiated module must be in the same directory as the
HDL code in which it is instantiated.
This section explains how to instantiate an XNF file as a black box in a
VHDL or Verilog design.
1.
“begin” line. Give the inserted code an instance name. Edit the
code to connect the signals in the design to the ports of the Logi-
BLOX module.
Synthesis
errors. Then save the design and close the HDL Editor.
synthesized (click the Synthesis button on the Flow tab).
Design”through the “Programming the Device” sections under
the “All-HDL Designs” section.
To attach an XNF module in the VHDL or Verilog code, use the
nets named in the PIN records and/or SIG records in the XNF file
as the port names of the component instantiation. The following
is an example XNF file with PIN and SIG records.
SYM, current_state_reg<4>, DFF, LIBVER=2.0.0
PIN, D, I, next_state<4>, ,
PIN, C, I, N10, ,
PIN, Q, O, current_state<4>, ,
END
SIG, current_state<4>
SIG, CLK, I, ,
SIG, DATA, I, ,
SIG, SYNCFLG, O, ,
To reference buses in the instantiation of XNF modules, the nets
named in PIN records and/or SIG records must be of the form.
netname<number>
Check Syntax in the HDL Editor. Correct any
Xilinx Development System

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