DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 23

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Chapter 6
Foundation Series 2.1i User Guide
HDL Designs with State Machines................................................. 5-21
HDL Designs with Instantiated Xilinx Unified Library Components 5-24
HDL Designs with Black Box Instantiation ..................................... 5-25
Schematic Designs in the HDL Flow.............................................. 5-49
HDL Design Entry and Synthesis
HDL File Selection ......................................................................... 6-1
Synthesis of HDL Modules............................................................. 6-5
Managing Large Designs ............................................................... 6-9
Design Partitioning Guidelines ....................................................... 6-10
User Libraries for HDL Flow Projects............................................. 6-11
Performing HDL Behavioral Simulation (Optional).................... 5-5
Synthesizing the Design ........................................................... 5-5
Express Constraints Editor ....................................................... 5-8
Express Time Tracker............................................................... 5-10
Performing Functional Simulation ............................................. 5-12
Implementing the Design .......................................................... 5-15
Editing Implementation Constraints .......................................... 5-17
Verifying the Design.................................................................. 5-20
Programming the Device .......................................................... 5-21
Creating a State Machine Macro .............................................. 5-21
LogiBLOX Modules in a VHDL or Verilog Design ..................... 5-26
CORE Generator COREs in a VHDL or Verilog Design ........... 5-36
XNF file in a VHDL or Verilog Design ....................................... 5-48
Adding a Schematic Library ...................................................... 5-49
Creating HDL Macros ............................................................... 5-50
Creating the Schematic and Generating a Netlist..................... 5-51
Selecting a Netlist Format......................................................... 5-52
Completing the design .............................................................. 5-52
Adding the File to the Project.................................................... 6-3
Removing Files from the Project............................................... 6-3
Getting Help with the Language................................................ 6-3
Schematic Flow Methodology ................................................... 6-5
HDL Flow Methodology............................................................. 6-7
Design Optimization.................................................................. 6-9
Setting Constraints Prior to Synthesis ...................................... 6-10
Performing a Static Timing Analysis .................................... 5-20
Performing a Timing Simulation........................................... 5-20
VHDL Instantiation............................................................... 5-26
Verilog Instantiation ............................................................. 5-31
VHDL Instantiation............................................................... 5-36
Verilog Instantiation ............................................................. 5-42
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