DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 292

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
B-20
The next UCF example illustrates the use of both global constraints
(PERIOD, OFFSET) to generally constrain the design and detailed
Timespecs (FROM:THRU:TO) to provide fast and slow exceptions to
the general timing requirements. Because the amount of constraints
placed on a design directly impact runtime, Xilinx recommends that
you first apply global constraints, then apply individual constraints
only to those elements of the design that require additional
constraints (or an exception to a constraint). The more global the
constraints, the better the runtime performance of the tools.
TS01 = MAXDELAY FROM TIMEGRP “PADS” TO TIMEGRP “PADS”
SCHEMATIC END;
# Sample UCF file
# Specify target device and package
CONFIG PART = XC4010e-PQ208-3 ;
# Global constraints
NET CLK1 PERIOD = 40 ;
NET DATA_OUT* OFFSET = OUT 15 AFTER DCLK ;
TIMESPEC TS01 = FROM PADS TO PADS
# Layout constraints
NET SCLINF LOC = P125 ;
# Detailed constraints
# Exception to cover X_DAT and Y_DAT buses
# Ignore timing on reset net
NET RESET_N TIG ;
# Slow exception for data leaving INA FFs
TIMESPEC TS02 = FROM FFS(INA*) TO FFS
# Faster timing required for data leaving RAM
TIMESPEC TS03 = FROM RAMS TO FFS 20 ;
# Form special timegroups related to RAMs
INST $1I64 TNM = SPDRAM ;
NET RAMBUS0 TPTHRU = RAMVIA ;
NET RAMBUS1 TPTHRU = RAMVIA ;
# Specify timing for this special timing path
40000 pS PRIORITY 0;
Xilinx Development System
40 ;
80 ;