LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 92

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

1
Port Integration Module (S12XSPIMV1)
2.3.27
92
Address 0x0249
Read: Anytime.
Write:Never, writes to this register have no effect.
Field
PTS
PTS
PTS
PTS
Reset
3
2
1
0
W
R
Port S general purpose input/output data—Data Register, SCI1 TXD output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port S general purpose input/output data—Data Register, SCI1 RXD input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port S general purpose input/output data—Data Register, SCI0 TXD output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port S general purpose input/output data—Data Register, SCI0 RXD input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
• The SCI0 function takes precedence over the general purpose I/O function if enabled.
• The SCI0 function takes precedence over the general purpose I/O function if enabled.
PTIS7
Port S Input Register (PTIS)
u
7
= Unimplemented or Reserved
PTIS6
Table 2-23. PTS Register Field Descriptions (continued)
u
6
Figure 2-25. Port S Input Register (PTIS)
S12XS Family Reference Manual, Rev. 1.11
PTIS5
u
5
PTIS4
u
4
Description
u = Unaffected by reset
PTIS3
3
u
PTIS2
u
2
Freescale Semiconductor
PTIS1
u
1
Access: User read
PTIS0
u
0
1