LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 206

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

S12X Debug (S12XDBGV3) Module
The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.3
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
by setting the comparator enable bit in the associated DBGXCTL control register.
206
Address: 0x0027
SC[3:0]
SC[3:0]
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SC[3:0]
0000
0001
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
Table 6-22. State2 —Sequencer Next State Selection (continued)
= Unimplemented or Reserved
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
0
0
6
Table 6-24. State3 — Sequencer Next State Selection
Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
Figure 6-1
Match3 triggers to Final State....... Other matches have no effect
Table 6-23. DBGSCR3 Field Descriptions
Match2 triggers to State1..... Match3 trigger to Final State
S12XS Family Reference Manual, Rev. 1.11
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Table 6-39
0
0
5
and described in
dictate that in the case of simultaneous matches, the match
Any match triggers to state1
Any match triggers to state2
0
0
4
Description
Description
Description
Section
SC3
0
3
6.3.2.8.1”. Comparators must be enabled
SC2
0
2
Freescale Semiconductor
SC1
0
1
SC0
0
0