LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 438

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

Serial Peripheral Interface (S12SPIV5)
15.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
15.2.4
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
15.3
This section provides a detailed description of address space and registers used by the SPI.
15.3.1
The memory map for the SPI is given in
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
438
Reserved
Reserved
Register
SPIDRH
SPICR1
SPICR2
SPIDRL
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
SPIBR
SPISR
Name
Memory Map and Register Definition
SS — Slave Select Pin
SCK — Serial Clock Pin
Module Memory Map
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
SPIE
SPIF
Bit 7
R15
T15
R7
T7
0
0
= Unimplemented or Reserved
SPPR2
XFRW
SPE
R14
T14
R6
T6
6
0
S12XS Family Reference Manual, Rev. 1.11
Figure 15-2. SPI Register Summary
Figure
SPPR1
SPTEF
SPTIE
R13
T13
R5
T5
5
0
15-2. The address listed for each register is the sum of a
MODFEN
SPPR0
MSTR
MODF
R12
T12
R4
T4
4
BIDIROE
CPOL
R11
T11
R3
T3
3
0
0
CPHA
SPR2
R10
T10
R2
T2
2
0
0
Freescale Semiconductor
SPISWAI
SSOE
SPR1
R9
R1
T9
T1
1
0
LSBFE
SPC0
SPR0
Bit 0
R8
T8
R0
T0
0