LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 223

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

6.4.5.3
Referring to
INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step.
The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst
tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0]
is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other
DBGCNT bits are incremented on each trace buffer entry.
When a COF occurs a trace buffer entry is made and the corresponding CDV bit is set.
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL )
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte3 and the byte at the higher address is stored to byte2
Freescale Semiconductor
Other Modes
S12XCPU
CPU12X
Mode
Detail
Table
Trace Buffer Organization
CXINF1
CXINF2
CINF1
CINF3
6-40. ADRH, ADRM, ADRL denote address high, middle and low byte respectively.
7
CADRH1
CADRH2
CPCH1
CPCH3
6
S12XS Family Reference Manual, Rev. 1.11
Table 6-40. Trace Buffer Organization
CADRM1
CADRM2
CPCM1
CPCM3
5
8-Byte Wide Word Buffer
CADRL1
CADRL2
CPCL1
CPCL3
4
CDATAH1
CDATAH2
CINF0
CINF2
3
CDATAL1
CDATAL2
CPCH0
CPCH2
2
S12X Debug (S12XDBGV3) Module
CPCM0
CPCM2
1
CPCL0
CPCL2
0
223