LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 673

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

A.2
This section describes the characteristics of the analog-to-digital converter.
A.2.1
The
The following constraints exist to obtain full-scale, full range results:
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
1
2
3
A.2.2
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.2.2.1
PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
Freescale Semiconductor
Conditions are shown in
Num C
Full accuracy is not guaranteed when differential voltage is less than 4.50 V
When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
1
2
3
4
5
6
7
8
Table A-14
D Reference potential
D Voltage difference V
D Voltage difference V
C Differential reference voltage
C ATD Clock Frequency (derived from bus clock via the
P ATD Clock Frequency in Stop mode (internal generated
D ADC conversion in stop, recovery time
D
V
SSA
prescaler bus)
temperature and voltage dependent clock, ICLK)
ATD Conversion Period
12 bit resolution:
10 bit resolution:
8 bit resolution:
ATD Characteristics
ATD Operating Characteristics
Factors Influencing Accuracy
Low
High
Port AD Output Drivers Switching
≤ V
and
RL
≤ V
Table A-15
Table A-4
IN
DDX
SSX
≤ V
3
unless otherwise noted, supply voltage 3.13 V < V
to V
to V
Rating
RH
Table A-14. ATD Operating Characteristics
show conditions under which the ATD operates.
SSA
DDA
1
S12XS Family Reference Manual, Rev. 1.11
≤ V
DDA
2
.
t
ATDSTPRCV
N
N
V
Symbol
N
f
∆
∆
ATDCLk
RH
CONV12
CONV10
CONV8
V
V
VDDX
VSSX
RH
RL
-V
RL
V
–2.35
V
–0.1
3.13
0.25
DDA
DDA
Min
0.6
20
19
17
SSA
—
/2
< 5.5 V
Typ
5.0
—
—
—
—
—
—
—
0
0
1
Electrical Characteristics
V
V
Max
DDA
0.1
0.1
5.5
8.3
1.7
1.5
42
41
39
DDA
/2
cycles
clock
MHz
MHz
Unit
ATD
µs
V
V
V
V
V
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