LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 41

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

1.2.3
1.2.3.1
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the oscillator output.
1.2.3.2
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state. As an output it is driven low to indicate when any internal MCU reset source triggers.
The RESET pin has an internal pull-up device.
1.2.3.3
This input only pin is reserved for factory test. This pin has a pull-down device.
1.2.3.4
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.2.3.5
PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital
converter ATD0.
1.2.3.6
PA[7:0] are general-purpose input or output pins.
1.2.3.7
PB[7:0] are general-purpose input or output pins.
Freescale Semiconductor
Detailed Signal Descriptions
EXTAL, XTAL — Oscillator Pins
RESET — External Reset Pin
TEST — Test Pin
BKGD / MODC — Background Debug and Mode Pin
PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD0
PA[7:0] — Port A I/O Pins
PB[7:0] — Port B I/O Pins
The pin list of the largest package version of each S12XS Family derivative
gives the complete of interface signals that also exist on smaller package
options, although some of them are not bonded out. For devices assembled
in smaller packages all non-bonded out pins should be configured as outputs
after reset in order to avoid current drawn from floating inputs. Refer to
Table 1-6
The TEST pin must be tied to V
for affected pins.
S12XS Family Reference Manual, Rev. 1.11
SS
NOTE
NOTE
in all applications.
Device Overview S12XS Family
41