LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 495

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

17.3.2
This section describes all the VREG_3V3 registers and their individual bits.
17.3.2.1
The VREGHTCL register allows to configure the VREG temperature sense features.
Freescale Semiconductor
0x02F0
Reserved
Reset
HTEN
HTDS
VSEL
Field
HTIE
HTIF
VAE
7, 6
5
4
3
2
1
0
W
R
Register Descriptions
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
Voltage Access Select Bit — If set, the bandgap reference voltage V
multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabled by bit VAE.
See device level specification for connectivity.
0 An internal temperature proportional voltage V
1 Bandgap reference voltage V
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specification for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
1 Voltage selected by VSEL can be accessed internally.
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
High Temperature Detect Status Bit —
This read-only status bit reflects the temperature status. Writes have no effect.
0 Temperature T
1 Temperature T
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag
HTIF is set to 1 when HTDS status bit changes. This flag can only be cleared by writing a 1.}Writing a 0 has no
effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
H
0
0
7
to Digital Converter channel).
igh
T
emperature
= Unimplemented or Reserved
0
0
6
DIE
DIE
is below level T
is above level T
Table 17-4. VREGHTCL Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
VSEL
0
5
Control Register (VREGHTCL)
BG
can be accessed internally if VAE is set.
HTID
HTIA
or RPM or Shutdown Mode.
and FPM.
VAE
1
4
Description
HT
can be accessed internally if VAE is set.
HTEN
0
3
BG
HTDS
can be accessed internally (i.e.
0
2
Voltage Regulator (S12VREGL3V3V1)
HTIE
0
1
HTIF
0
0
495