LFDAS12XSDT Freescale Semiconductor, LFDAS12XSDT Datasheet - Page 654

• Manufacturer Part Number: LFDAS12XSDT
• Description: HARDWARE MC9S12XS 52-PIN
• Manufacturer: Freescale Semiconductor

Specifications of LFDAS12XSDT

• Module/board Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: -

64 KByte Flash Module (S12XFTMR64K1V1)
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to
(FCNFG)”,
Status Register
The logic used for generating the Flash module interrupts is shown in
20.4.4
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see
20.4.5
If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation
will be completed before the CPU is allowed to enter stop mode.
20.5
The Flash module provides security information to the MCU. The Flash security state is defined by the
SEC bits of the FSEC register (see
register using data read from the security byte of the Flash configuration field at global address
0x7F_FF0F.
The security state out of reset can be permanently changed by programming the security byte of the Flash
configuration field. This assumes that you are starting from a mode where the necessary P-Flash erase and
program commands are available and that the upper region of the P-Flash is unprotected. If the Flash
security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
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Unsecuring the MCU using Backdoor Key Access
Unsecuring the MCU in Special Single Chip Mode using BDM
Mode and Security Effects on Flash Command Availability
Security
Section 20.3.2.6, “Flash Error Configuration Register
Wait Mode
Stop Mode
(FSTAT)”, and
DFDIE
DFDIF
SFDIE
SFDIF
CCIE
CCIF
Figure 20-27. Flash Module Interrupts Implementation
Section 20.3.2.8, “Flash Error Status Register
S12XS Family Reference Manual, Rev. 1.11
Table
Section 20.4.3,
20-10). During reset, the Flash module initializes the FSEC
Section 20.3.2.5, “Flash Configuration Register
“Interrupts”).
Flash Command Interrupt Request
Flash Error Interrupt Request
(FERCNFG)”,
Figure
20-27.
(FERSTAT)”.
Section 20.3.2.7, “Flash
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