AC162078 Microchip Technology, AC162078 Datasheet - Page 62

• Manufacturer Part Number: AC162078
• Description: HEADER INTRFC MPLAB ICD2 18F1330
• Manufacturer: Microchip Technology

Specifications of AC162078

• Accessory Type: Transition Header
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICD2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

PIC18F1230/1330
TABLE 6-2:
DS39758D-page 62
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
BAUDCON
CVRCON
CMCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
PTCON0
PTCON1
Legend:
Note 1:
File Name
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads
as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
Section 3.6.4 “PLL in INTOSC Modes”.
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as
‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
A/D Result Register High Byte
A/D Result Register Low Byte
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
EUSART Receive Register
EUSART Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
TMR0ON
ABDOVF
SEVTEN
PTOPS3
OSCFIP
OSCFIF
OSCFIE
INTSRC
CVREN
C2OUT
EEPGD
IDLEN
ADFM
CSRC
SPEN
PTEN
RD16
IPEN
Bit 7
—
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
SBOREN
PLLEN
T016BIT
PTOPS2
T1RUN
C1OUT
RCIDL
PTDIR
IRCF2
CFGS
ADIP
ADIF
ADIE
Bit 6
RX9
TX9
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(1)
T1CKPS1
PTOPS1
RXDTP
C0OUT
ACQT2
IRCF1
IRVST
CVRR
TXEN
SREN
T0CS
RCIP
RCIF
RCIE
Bit 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1CKPS0
PTOPS0
CVRSS
VCFG0
ACQT1
TXCKP
LVDEN
IRCF0
SYNC
CREN
FREE
TUN4
T0SE
EEIP
EEIE
Bit 4
PTIP
PTIF
PTIE
EEIF
TXIP
TXIF
TXIE
—
RI
—
—
—
N
T1OSCEN
PTCKPS1
WRERR
CMP2IP
CMP2IE
CMP2IF
SENDB
ADDEN
PCFG3
ACQT0
BRG16
LVDL3
OSTS
CVR3
CHS1
TUN3
Bit 3
PSA
OV
TO
—
—
—
—
—
—
—
—
—
PTCKPS0
T1SYNC
CMP1IP
CMP1IF
CMP1IE
CMEN2
PCFG2
ADCS2
T0PS2
LVDL2
WREN
BRGH
LVDIP
LVDIE
CHS0
CVR2
FERR
LVDIF
TUN2
IOFS
Bit 2
PD
—
—
—
—
—
—
Z
GO/DONE
TMR1CS
PTMOD1
CMP0IP
CMP0IF
CMP0IE
CMEN1
PCFG1
ADCS1
T0PS1
LVDL1
OERR
CVR1
TRMT
SCS1
TUN1
WUE
Bit 1
POR
WR
DC
—
—
—
—
—
—
—
—
 2009 Microchip Technology Inc.
SWDTEN
TMR1ON
PTMOD0
TMR1IP
TMR1IF
TMR1IE
ABDEN
CMEN0
PCFG0
ADCS0
T0PS0
LVDL0
ADON
SCS0
CVR0
TX9D
RX9D
TUN0
Bit 0
BOR
RD
—
—
—
—
—
—
—
C
(7)
01-0 00-00
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0100 q000
--00 0101
---- ---0
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0--- 0000
---0 1111
0-00 0000
0-00 0000
000- -000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
xx-0 x000
---1 ----
---0 ----
---0 ----
1--1 -1--
0--0 -0--
0--0 -0--
-111 1111
-000 0000
-000 0000
00-0 0000
0000 0000
00-- ----
POR, BOR
Value on
Details
48, 109
48, 109
48, 107
48, 187
48, 203
48, 115
48, 115
48, 178
48, 178
48, 169
48, 170
48, 171
48, 150
48, 184
48, 179
48, 152
48, 152
48, 160
48, 157
48, 148
48, 149
49, 103
49, 101
49, 103
49, 101
49, 102
49, 100
49, 122
49, 122
48, 111
48, 64
48, 28
48, 40
49, 81
49, 81
49, 72
48, 73
49, 99
49, 99
49, 98
49, 25
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