AC162078 Microchip Technology, AC162078 Datasheet - Page 61

• Manufacturer Part Number: AC162078
• Description: HEADER INTRFC MPLAB ICD2 18F1330
• Manufacturer: Microchip Technology

Specifications of AC162078

• Accessory Type: Transition Header
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICD2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

TABLE 6-2:
 2009 Microchip Technology Inc.
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
Legend:
Note 1:
File Name
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads
as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
Section 3.6.4 “PLL in INTOSC Modes”.
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as
‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
Indirect Data Memory Address Pointer 2 Low Byte
STKFUL
GIE/GIEH
INT2IP
RBPU
Bit 7
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F1230/1330)
(5)
STKUNF
PEIE/GIEL
INTEDG0
INT1IP
Bit 6
—
—
—
—
—
—
—
(5)
INTEDG1
TMR0IE
INT3IE
bit 21
Bit 5
—
—
—
—
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INTEDG2
INT0IE
INT2IE
Bit 4
SP4
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
Indirect Data Memory Address Pointer 1 High Byte
Bank Select Register
Indirect Data Memory Address Pointer 2 High Byte
INTEDG3
INT1IE
RBIE
Bit 3
SP3
TMR0IP
TMR0IF
INT3IF
Bit 2
SP2
PIC18F1230/1330
INT3IP
INT0IF
INT2IF
Bit 1
SP1
INT1IF
RBIP
Bit 0
RBIF
SP0
DS39758D-page 61
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
---- 0000
xxxx xxxx
xxxx xxxx
---- 0000
xxxx xxxx
---- 0000
---- 0000
xxxx xxxx
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Details
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on