AC162078 Microchip Technology, AC162078 Datasheet - Page 135

HEADER INTRFC MPLAB ICD2 18F1330

AC162078

Manufacturer Part Number
AC162078
Description
HEADER INTRFC MPLAB ICD2 18F1330
Manufacturer
Microchip Technology
Datasheet

Specifications of AC162078

Accessory Type
Transition Header
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
ICD2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable

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Part Number:
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14.7
In power inverter applications, where the PWMs are
used in Complementary mode to control the upper and
lower switches of a half-bridge, a dead-time insertion is
highly recommended. The dead-time insertion keeps
both outputs in inactive state for a brief time. This
avoids any overlap in the switching during the state
change of the power devices due to T
characteristics.
Because the power output devices cannot switch
instantaneously, some amount of time must be
provided between the turn-off event of one PWM output
in a complementary pair and the turn-on event of the
other transistor. The PWM module allows dead time to
be programmed. The following sections explain the
dead-time block in detail.
FIGURE 14-17:
FIGURE 14-18:
 2009 Microchip Technology Inc.
Compare Input
Duty Cycle
Dead-Time Generators
Dead Time
Dead Time
Select Bits
Prescale
F
OSC
DEAD-TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR
DEAD-TIME INSERTION FOR COMPLEMENTARY PWM
and Prescaler
Clock Control
Compare
Output
PWM1
PWM0
PDC1
ON
and T
Dead-Time Register
6-Bit Down Counter
Zero Compare
OFF
t d
14.7.1
Each complementary output pair for the PWM module
has a 6-bit down counter used to produce the dead-
time insertion. As shown in Figure 14-17, each dead-
time unit has a rising and falling edge detector
connected to the duty cycle comparison output. The
dead time is loaded into the timer on the detected PWM
edge event. Depending on whether the edge is rising or
falling, one of the transitions on the complementary
outputs is delayed until the timer counts down to zero.
A timing diagram, indicating the dead-time insertion for
one pair of PWM outputs, is shown in Figure 14-18.
t d
PIC18F1230/1330
DEAD-TIME INSERTION
Odd PWM Signal to
Output Control Block
Even PWM Signal to
Output Control Block
DS39758D-page 135

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