AC162078 Microchip Technology, AC162078 Datasheet - Page 109

• Manufacturer Part Number: AC162078
• Description: HEADER INTRFC MPLAB ICD2 18F1330
• Manufacturer: Microchip Technology

Specifications of AC162078

• Accessory Type: Transition Header
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICD2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

12.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0
register is written, the increment is inhibited for the
following two instruction cycles. The user can work
around this by writing an adjusted value to the TMR0
register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI/AN2/V
The incrementing edge is determined by the Timer0
Source Edge Select bit (T0SE). Clearing the T0SE bit
selects the rising edge.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
12.2
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions writ-
ing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0,
BSF TMR0, x..., etc.) will clear the prescaler count.
TABLE 12-1:
 2009 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1:
Note:
Name
Timer0 Operation
Prescaler
RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in CONFIG1H.
Writing to TMR0, when the prescaler is
assigned
prescaler count but will not change the
prescaler assignment.
OSC
Timer0 Register Low Byte
Timer0 Register High Byte
GIE/GIEH
TMR0ON
REGISTERS ASSOCIATED WITH TIMER0
). Also, there is a delay in the actual
RA7
Bit 7
(1)
to
Timer0,
PEIE/GIEL TMR0IE
T016BIT
RA6
Bit 6
(1)
will
PORTA Data Direction Control Register
clear
T0CS
Bit 5
REF
the
+.
INT0IE
T0SE
Bit 4
12.2.1
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
12.3
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep
mode, since the timer requires clock cycles even when
T0CS is set.
12.4
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 12-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This
provides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
RBIE
Bit 3
PSA
Timer0 Interrupt
16-Bit Mode Timer Reads and
Writes
PIC18F1230/1330
TMR0IF
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
INT0IF
T0PS1
Bit 1
T0PS0
RBIF
Bit 0
DS39758D-page 109
Values on
Reset
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