AC162078 Microchip Technology, AC162078 Datasheet - Page 208

HEADER INTRFC MPLAB ICD2 18F1330

AC162078

Manufacturer Part Number
AC162078
Description
HEADER INTRFC MPLAB ICD2 18F1330
Manufacturer
Microchip Technology
Datasheet

Specifications of AC162078

Accessory Type
Transition Header
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
ICD2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AC162078
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC18F1230/1330
20.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPx bits have no direct
effect. CPx bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTx Configuration bit is ‘0’. The EBTRx
bits control table reads. For a block of user memory
with the EBTRx bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 20-6:
DS39758D-page 208
Results: All table writes disabled to Blockn whenever WRTx = 0.
TBLPTR = 0008FFh
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 000FFEh
PC = 001800h
TABLE WRITE (WRTx) DISALLOWED
Program Memory
TBLWT*
TBLWT*
A table read instruction that executes from a location
outside of that block is not allowed to read and will result
in reading ‘0’s. Figures 20-6 through 20-8 illustrate table
write and table read protection.
Note:
000000h
0007FFh
000800h
000FFFh
001000h
001FFFh
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP operation or an
external programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
 2009 Microchip Technology Inc.

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