AC162078 Microchip Technology, AC162078 Datasheet - Page 226
![HEADER INTRFC MPLAB ICD2 18F1330](/photos/8/98/89869/ac162078_sml.jpg)
AC162078
Manufacturer Part Number
AC162078
Description
HEADER INTRFC MPLAB ICD2 18F1330
Manufacturer
Microchip Technology
Datasheet
1.AC162078.pdf
(318 pages)
Specifications of AC162078
Accessory Type
Transition Header
Lead Free Status / RoHS Status
Not applicable / Not applicable
For Use With/related Products
ICD2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Not applicable / Not applicable
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AC162078
Manufacturer:
MICROCHIP
Quantity:
12 000
- Current page: 226 of 318
- Download datasheet (3Mb)
PIC18F1230/1330
BNOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39758D-page 226
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Overflow
If Overflow
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Overflow
BNOV
-128 n 127
if Overflow bit is ‘0’,
(PC) + 2 + 2n PC
None
If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
Q2
No
‘n’
‘n’
=
=
=
=
=
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
n
0101
BNOV Jump
operation
Process
Process
Data
Data
Q3
No
Q3
nnnn
operation
operation
Write to
Q4
PC
Q4
No
No
nnnn
BNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
Q1
No
Q1
PC
If Zero
If Zero
PC
PC
Read literal
Read literal
operation
Branch if Not Zero
BNZ
-128 n 127
if Zero bit is ‘0’,
(PC) + 2 + 2n PC
None
If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
2009 Microchip Technology Inc.
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0001
BNZ
operation
Process
Process
Data
Data
Q3
No
Q3
Jump
nnnn
operation
operation
Write to
PC
Q4
No
Q4
No
nnnn
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