AC162078 Microchip Technology, AC162078 Datasheet - Page 105

• Manufacturer Part Number: AC162078
• Description: HEADER INTRFC MPLAB ICD2 18F1330
• Manufacturer: Microchip Technology

Specifications of AC162078

• Accessory Type: Transition Header
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICD2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

11.6
External interrupts on the RA0/INT0, RA1/INT1, RB2/
INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the pin, the corresponding flag
bit, INTxIF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxIE. Flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from Idle or Sleep modes if bit
INTxIE was set prior to going into those modes. If the
Global Interrupt Enable bit, GIE, is set, the processor
will branch to the interrupt vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
EXAMPLE 11-1:
 2009 Microchip Technology Inc.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTx Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
11.7
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh  00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L
register pair (FFFFh  0000h) will set TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 12.0 “Timer0 Module” for further details on
the Timer0 module.
11.8
An input change on PORTA<1:0> and/or PORTB<2:3>
sets flag bit, RBIF (INTCON<0>). The interrupt can be
enabled/disabled by setting/clearing enable bit, RBIE
(INTCON<3>). Interrupt priority for interrupt-on-change
is determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
11.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 6.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 11-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
TMR0 Interrupt
Interrupt-on-Change
Context Saving During Interrupts
PIC18F1230/1330
DS39758D-page 105