AC162078 Microchip Technology, AC162078 Datasheet - Page 259

• Manufacturer Part Number: AC162078
• Description: HEADER INTRFC MPLAB ICD2 18F1330
• Manufacturer: Microchip Technology

Specifications of AC162078

• Accessory Type: Transition Header
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICD2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / Not applicable

CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example:
 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PCLATH =
PCLATU =
W
PC
TOS
PCLATH =
PCLATU =
W
Q1
No
=
=
=
=
=
operation
Subroutine Call Using WREG
CALLW
None
(PC + 2)  TOS,
(W)  PCL,
(PCLATH)  PCH,
(PCLATU)  PCU
None
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, STATUS or BSR.
1
2
HERE
WREG
Read
0000
Q2
No
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
CALLW
0000
PUSH PC to
operation
stack
Q3
No
0001
operation
operation
Q4
No
No
0100
MOVSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
REG2
FSR2
Contents
of 85h
REG2
PIC18F1230/1330
Q1
source addr
No dummy
Determine
operation
Move Indexed to f
MOVSF [z
0  z
0  f
((FSR2) + z
None
The contents of the source register are
moved to destination register ‘f
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
2
2
MOVSF
d
’ in the second word. Both addresses
read
1110
1111
Q2
No
=
=
=
=
=
=
d
s
 4095
 127
s
’ in the first word to the value of
80h
33h
11h
80h
33h
33h
[05h], REG2
s
s
1011
ffff
], f
)  f
source addr
Determine
operation
d
Q3
No
d
DS39758D-page 259
0zzz
ffff
source reg
register ‘f’
(dest)
Read
Write
d
Q4
zzzz
ffff
’. The
s
d