Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 112

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Watchdog Timer Calibration
Watchdog Timer Reload Unlock Sequence
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT)
Register is set to 1. For more information about system reset, see
Recovery and Low Voltage Detection
WDT Reset in STOP Mode
If configured to generate a Reset when a time-out occurs and the device is in STOP Mode,
the Watchdog Timer initiates a Stop Mode Recovery. Both the WDT status bit and the
STOP bit in the Reset Status (RSTSTAT) Register are set to 1 following WDT time-out in
STOP Mode.
Writing the unlock sequence to the Watchdog Timer (WDTCTL) Control Register address
unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) to
allow changes to the time-out period. These write operations to the WDTCTL Register
address produce no effect on the bits in the WDTCTL Register. The locking mechanism
prevents spurious writes to the Reload registers. Observe the following steps to unlock the
Watchdog Timer Reload Byte registers (WDTU, WDTH and WDTL) for write access.
1. Write
2. Write
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU) with the appropriate
4. Write the Watchdog Timer Reload High Byte Register (WDTH) with the appropriate
5. Write the Watchdog Timer Reload Low Byte Register (WDTL) with the appropriate
All three Watchdog Timer Reload registers must be written in the order just listed. There
must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watchdog Timer Reload registers is loaded into the counter
when the Watchdog Timer is first enabled and every time a WDT instruction is executed.
Due to its extremely low operating current, the Watchdog Timer oscillator is somewhat
inaccurate. This variation can be corrected using the calibration data stored in the Flash
Information Page; see Tables 100 and 101 on page 173 for details. Loading these values
time-out value.
time-out value.
time-out value.
55H
AAH
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
P R E L I M I N A R Y
chapter on page 22.
Z8 Encore! XP
Watchdog Timer Calibration
Product Specification
the Reset, Stop Mode
®
F082A Series
95