Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 96

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
CAPTURE Mode
In CAPTURE Mode, the current timer count value is recorded when the appropriate exter-
nal Timer Input transition occurs. The Capture count value is written to the Timer PWM
High and Low Byte registers. The timer input is the system clock. The TPOL bit in the
Timer Control Register determines if the Capture occurs on a rising edge or a falling edge
of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the
timer continues counting. The INPCAP bit in TxCTL0 Register is set to indicate the timer
interrupt is because of an input capture event.
The timer continues counting up to the 16-bit reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an inter-
rupt and continues counting. The INPCAP bit in TxCTL0 Register clears indicating the
timer interrupt is not because of an input capture event.
Observe the following steps for configuring a timer for CAPTURE Mode and initiating
the count:
1. Write to the Timer Control Register to:
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these regis-
PWM Output High Time Ratio (%)
PWM Output High Time Ratio (%)
cally
ters allows the software to determine if interrupts were generated by either a capture
event or a reload. If the PWM High and Low Byte registers still contain 0000H after
the interrupt, the interrupt was generated by a Reload.
Disable the timer
Configure the timer for CAPTURE Mode
Set the prescale value
Set the Capture edge (rising or falling) for the Timer Input
0001H
).
P R E L I M I N A R Y
=
=
--------------------------------
Reload Value
Reload Value
------------------------------------------------------------------ -
PWM Value
Reload Value
100
PWM Value
Z8 Encore! XP
Product Specification
100
®
F082A Series
Operation
79

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