Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 79

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7:4]
[3:0]
PCxI
Note: x indicates the specific GPIO Port C pin number (0–3).
Interrupt Request 2 Register
IRQ0 Enable High and Low Bit Registers
Description
Reserved
These bits are reserved and must be programmed to 0000.
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
R/W
7
0
The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 Register to determine if any interrupt requests are pending.
Table 38 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters, shown in Tables 39 and 40, form a priority-encoded enabling for interrupts in the
Interrupt Request 0 Register.
Note: x indicates register bits 0–7.
IRQ0ENH[x]
R/W
6
0
Table 37. Interrupt Request 2 Register (IRQ2)
Table 38. IRQ0 Enable and Priority Encoding
0
0
1
1
Reserved
R/W
5
0
IRQ0ENL[x] Priority
P R E L I M I N A R Y
0
1
0
1
R/W
4
0
Disabled
Level 1
Level 2
Level 3
FC6H
PC3I
R/W
3
0
Description
High
Disabled
Low
Medium
Interrupt Control Register Definitions
Z8 Encore! XP
PC2I
R/W
2
0
Product Specification
PC1I
R/W
1
0
®
F082A Series
PC0I
R/W
0
0
62