Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet
Z8F041APH020SG2156
Specifications of Z8F041APH020SG2156
Related parts for Z8F041APH020SG2156
Z8F041APH020SG2156 Summary of contents
Page 1
... High-Performance 8-Bit Microcontrollers Z8 Encore! XP Series Product Specification PS022827-1212 ® Copyright ©2012 Zilog , Inc. All rights reserved. www.zilog.com ® F082A ...
Page 2
... HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS022827-1212 ...
Page 3
Revision History Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Date Level Chapter/Section Dec 27 Port ...
Page 4
Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Reset, Stop Mode Recovery and Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset Types . . ...
Page 6
LED Drive Level Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Architecture ...
Page 8
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
... Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Trim Bit Address 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Zilog Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Temperature Sensor Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Watchdog Timer Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Randomized Lot Identifier ...
Page 10
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
List of Figures Figure 1. Z8 Encore! XP F082A Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 Z8F08xA, Z8F04xA, Z8F02xA ...
Page 12
Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface; ...
Page 13
List of Tables Table 1. Z8 Encore! XP F082A Series Family Part Selection Guide . . . . . . . . . . . . . 2 Table 2. Signal Descriptions . . . . . . . . ...
Page 14
Table 29. Port A–C Input Data Registers (PxIN Table 30. Port ...
Page 15
Table 59. Watchdog Timer Control Register (WDTCTL Table 60. Watchdog Timer Reload Upper Byte Register (WDTU ...
Page 16
Table 89. Flash Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . 164 Table 90. Trim Options Bits at Address 0000H . . . . . . . . ...
Page 17
Table 119. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 18
... Overview Zilog’s Z8 Encore! MCU family of products are the first in a line of Zilog microcontroller products based upon the 8-bit eZ8 CPU. Zilog’s Z8 Encore! XP F082A Series products expand upon Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit pro- gramming capability allows for faster development time and program changes in the field. ...
Page 19
ports capable of direct LED drive with no current limit resistor required • On-Chip Debugger (OCD) • Voltage Brown-Out (VBO) protection • Programmable low battery detection (LVD) (8-pin devices only) • Bandgap generated precision voltage references ...
Page 20
Block Diagram Figure 1 displays the block diagram of the architecture of the Z8 Encore! XP F082A Series devices. eZ8 CPU Memory Busses Register Bus Timers UART Comparator IrDA GPIO Figure 1. Z8 Encore! XP F082A Series Block Diagram PS022827-1212 ...
Page 21
... CPU and Peripheral Overview The eZ8 CPU, Zilog’s latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The features of eZ8 CPU include: • Direct register-to-register architecture allows each register to function as an ...
Page 22
Internal Precision Oscillator The internal precision oscillator (IPO trimmable clock source that requires no exter- nal components. Temperature Sensor The optional temperature sensor produces an analog output proportional to the device tem- perature. This signal can be sent ...
Page 23
ONE-SHOT, CONTINUOUS, GATED, CAPTURE, CAPTURE RESTART, COMPARE, CAPTURE and COMPARE, PWM SINGLE OUTPUT and PWM DUAL OUTPUT modes. General-Purpose Input/Output The Product Line MCUs feature port pins (Ports A–D) for general- purpose input/ output (GPIO). ...
Page 24
The RESET pin is bidirectional, that is, it functions as reset source and as a reset indicator. PS022827-1212 Z8 Encore ® F082A Series Product Specification CPU ...
Page 25
Pin Description The Z8 Encore! XP F082A Series products are available in a variety of packages styles and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information about physical package ...
Page 26
PA0/T0IN/T0OUT/XIN//DBG PA1/T0OUT/X /ANA3/VREF/CLKIN OUT PA2/RESET/DE0/T1OUT Figure 2. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 8-Pin SOIC, QFN/MLF-S, or PDIP Package PB1/ANA1/AMPINN PB2/ANA2/AMPINP PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN PA1/T0OUT/X PA2/DE0 PA3/CTS0 PA4/RXD0 Figure 3. Z8F08xA, Z8F04xA, Z8F02xA and Z8F01xA in 20-Pin SOIC, SSOP or PDIP ...
Page 27
Signal Descriptions Table 2 describes the Z8 Encore! XP F082A Series signals. See the section on page 8 to determine the signals available for the specific package styles. Signal Mnemonic I/O Description General-Purpose I/O Ports A–D PA[7:0] I/O Port A. ...
Page 28
Table 2. Signal Descriptions (Continued) Signal Mnemonic I/O Description Analog ANA[7:0] I Analog Port. These signals are used as inputs to the analog-to-digital con- verter (ADC). VREF I/O Analog-to-digital converter reference voltage input, or buffered output for internal reference. Low-Power ...
Page 29
Table 2. Signal Descriptions (Continued) Signal Mnemonic I/O Description Reset RESET I/O RESET. Generates a Reset when asserted (driven Low). Also serves as a reset indicator; the Z8 Encore! XP forces this pin low when in reset. This pin is ...
Page 30
Table 3. Pin Characteristics (20- and 28-pin Devices) Symbol Reset Mnemonic Direction Direction AVDD N/A N/A AVSS N/A N/A DBG I/O I PA[7:0] I/O I PB[7:0] I/O I PC[7:0] I/O I RESET/ I/O I/O PD0 (defaults to RESET) VDD N/A ...
Page 31
Table 4. Pin Characteristics (8-Pin Devices) ) Symbol Reset Mnemonic Direction Direction PA0/DBG I/O I (but can change during reset if key sequence detected) PA1 I/O I RESET/ I/O I/O PA2 (defaults to RESET) PA[5:3] I N/A N/A ...
Page 32
... These three address spaces are covered briefly in the following subsections. For more information about eZ8 CPU and its address space, refer to the (UM0128), which is available for download on www.zilog.com. Register File The Register File address space in the Z8 Encore! MCU (4096 bytes). The Regis- ter File is composed of two sections: control registers and general-purpose registers ...
Page 33
Flash memory addresses returns unimplemented Program Memory addresses produces no effect. Table 5 describes the Pro- gram Memory Maps for the Z8 Encore! XP F082A Series products. Table 5. Z8 Encore! XP F082A Series Program Memory ...
Page 34
... Reserved Oscillator Fail Trap Vectors Program Memory to . When the Information Area access is FE00H FF7FH Function Zilog Option Bits/Calibration Data Part Number 20-character ASCII alphanumeric code Left-justified and filled with FFH Reserved Zilog Calibration Data Reserved ® ...
Page 35
Register Map Table 7 provides the address map for the Register File of the Z8 Encore! XP F082A Series devices. Not all devices and package styles in the Z8 Encore! XP F082A Series support the ADC, or all of the ...
Page 36
Table 7. Register File Address Map (Continued) Address (Hex) Register Description Timer 1 F08 Timer 1 High Byte F09 Timer 1 Low Byte F0A Timer 1 Reload High Byte Timer 1 (cont’d) F0B Timer 1 Reload Low Byte F0C Timer ...
Page 37
Table 7. Register File Address Map (Continued) Address (Hex) Register Description F85 Reserved Oscillator Control F86 Oscillator Control F87–F8F Reserved Comparator 0 F90 Comparator 0 Control F91–FBF Reserved Interrupt Controller FC0 Interrupt Request 0 FC1 IRQ0 Enable High Bit FC2 ...
Page 38
Table 7. Register File Address Map (Continued) Address (Hex) Register Description FD9 Port C Control FDA Port C Input Data FDB Port C Output Data GPIO Port D FDC Port D Address FDD Port D Control FDE Reserved FDF Port ...
Page 39
Reset, Stop Mode Recovery and Low Voltage Detection The Reset Controller within the Z8 Encore! XP F082A Series controls Reset and Stop Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause ...
Page 40
Table 8. Reset and Stop Mode Recovery Characteristics and Latency Reset Type Control Registers System Reset Reset (as applicable) System Reset with Crystal Reset (as applicable) Oscillator Enabled Stop Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers Stop Mode Recovery ...
Page 41
Reset Sources Table 9 lists the possible sources of a system reset. Table 9. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset/Voltage Brown- modes Out Watchdog Timer time-out when configured for Reset RESET ...
Page 42
V POR V VBO Internal Precision Oscillator Crystal Oscillator Internal RESET signal Note: Not to Scale Voltage Brown-Out Reset The devices in the Z8 Encore! XP F082A Series provide low Voltage Brown-Out (VBO) protection. The ...
Page 43
VCC = 3 POR V VBO Program Execution System Clock Internal RESET signal Note: Not to Scale Figure 6. Voltage Brown-Out Reset Operation The POR level is greater than the VBO level by the specified hysteresis value. This ...
Page 44
A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! XP F082A ...
Page 45
Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT) Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions. The text following provides more detailed information about each of ...
Page 46
Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! XP F082A Series device is in STOP Mode and the external RESET pin is driven Low, a system reset ...
Page 47
Table 11. Reset Status Register (RSTSTAT) Bit 7 6 Field POR STOP RESET See descriptions below R Address Bit Description [7] Power-On Reset Indicator POR If this bit is set Power-On Reset event occurs. This ...
Page 48
Table 12. Reset and Stop Mode Recovery Bit Descriptions Reset or Stop Mode Recovery Event Power-On Reset Reset using RESET pin assertion Reset using Watchdog Timer time-out Reset using the On-Chip Debugger (OCTCTL[1] set to 1) Reset from STOP Mode ...
Page 49
Low-Power Modes The Z8 Encore! XP F082A Series products contain power-saving features. The highest level of power reduction is provided by the STOP Mode, in which nearly all device func- tions are powered down. The next lower level of power ...
Page 50
HALT Mode Executing the eZ8 CPU’s HALT instruction places the device into HALT Mode, which powers down the CPU but leaves all other peripherals active. In HALT Mode, the operat- ing characteristics are: • Primary oscillator is enabled and continues ...
Page 51
OFF. To use the LPO, clear the LPO bit, turning it ON. Clearing this bit might interfere with normal ADC measurements on ANA0 (the LPO out- put). This bit enables the amplifier even in STOP Mode. ...
Page 52
Note: Asserting any power control bit disables the targeted block regardless of any enable bits contained in the target block’s control registers. PS022827-1212 Z8 Encore Power Control Register ...
Page 53
General-Purpose Input/Output The Z8 Encore! XP F082A Series products support a maximum of 25 port pins (Ports A– D) for general-purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output ...
Page 54
Architecture Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not dis- played. System Port Output Data Register DATA D Q ...
Page 55
... See details. Caution: For pins with multiple alternate functions, Zilog recommends writing to the AFS1 and AFS2 subregisters before enabling the alternate function via the AF subregister re- sult, spurious transitions through unwanted alternate function modes will be prevented. ...
Page 56
Shared Debug Pin On the 8-pin version of this device only, the Debug pin shares function with the PA0 GPIO pin. This pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during ...
Page 57
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) Port Pin Mnemonic 1,2 Port A PA0 T0IN/T0OUT Reserved PA1 T0OUT Reserved PA2 DE0 Reserved PA3 CTS0 Reserved PA4 RXD0/IRRX0 Reserved PA5 TXD0/IRTX0 Reserved PA6 T1IN/T1OUT Reserved PA7 T1OUT Reserved Notes: ...
Page 58
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued) Port Pin Mnemonic 3 Port B PB0 Reserved ANA0/AMPOUT PB1 Reserved ANA1/AMPINN PB2 Reserved ANA2/AMPINP PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved 4 V REF PB6 Reserved Reserved PB7 ...
Page 59
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued) Port Pin Mnemonic 5 Port C PC0 Reserved ANA4/CINP PC1 Reserved ANA5/CINN PC2 Reserved 4 ANA6/V REF PC3 COUT Reserved PC4 Reserved PC5 Reserved PC6 Reserved PC7 Reserved 6 Port ...
Page 60
Table 16. Port Alternate Function Mapping (8-Pin Parts) Port Pin Mnemonic Port A PA0 T0IN Reserved Reserved T0OUT PA1 T0OUT Reserved CLKIN Analog Functions PA2 DE0 RESET T1OUT Reserved PA3 CTS0 COUT T1IN Analog Functions PA4 RXD0 Reserved Reserved Analog ...
Page 61
GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con- figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other ...
Page 62
Port A–D Address Registers The Port A–D Address registers select the GPIO port functionality accessible through the Port A–D Control registers. The Port A–D Address and Control registers combine to pro- vide access to all GPIO port controls; see Tables ...
Page 63
Port A–D Control Registers The Port A–D Control registers set the GPIO port operation. The value in the correspond- ing Port A–D Address Register determines which subregister is read from or written Port A–D Control Register transaction; ...
Page 64
Port A–D Alternate Function Subregisters The Port A–D Alternate Function Subregister, shown in Table 22, is accessed through the Port A–D Control Register by writing D Alternate Function subregisters enable the alternate function selection on pins. If dis- abled, pins ...
Page 65
Table 23. Port A–D Output Control Subregisters (PxOC) Bit 7 6 Field POC7 POC6 RESET R/W R/W R/W Address If 03H in Port A–D Address Register, accessible through the Port A–D Control Register Bit Description [7:0] Port Output Control POCx ...
Page 66
Port A–D Stop Mode Recovery Source Enable Subregisters The Port A–D Stop Mode Recovery Source Enable Subregister, shown in Table 25, is accessed through the Port A–D Control Register by writing Register. Setting the bits in the Port A–D Stop ...
Page 67
Port A–D Pull-up Enable Subregisters The Port A–D Pull-up Enable Subregister, shown in Table 26, is accessed through the Port A–D Control Register by writing the Port A–D Pull-up Enable subregisters enables a weak internal resistive pull-up on the specified ...
Page 68
Table 27. Port A–D Alternate Function Set 1 Subregisters (PxAFS1) Bit 7 6 Field PAFS17 PAFS16 RESET 0 0 R/W R/W R/W Address If 07H in Port A–D Address Register, accessible through the Port A–D Control Register Bit Description [7:0] ...
Page 69
Port A–C Input Data Registers Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled values from the corresponding port pins. The Port A–C Input Data registers are read-only. The value returned for any unused ...
Page 70
LED Drive Enable Register The LED Drive Enable Register, shown in Table 31, activates the controlled current drive. The Alternate Function Register has no control over the LED function; therefore, setting the Alternate Function Register to select the LED function ...
Page 71
LED Drive Level Low Register The LED Drive Level registers contain two control bits for each Port C pin (Table 33). These two bits select between four programmable drive levels. Each pin is individually programmable. Table 33. LED Drive Level ...
Page 72
... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information about interrupt servicing by the eZ8 CPU, refer to the available for download on www.zilog.com. Interrupt Vector Listing Table 34 lists all of the interrupts available in order of priority. The interrupt vector is stored with the most-significant byte (MSB) at the even Program Memory address and the least-significant byte (LSB) at the following odd Program Memory address ...
Page 73
Table 34. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see Watchdog Timer) 003AH Primary Oscillator Fail Trap (not an interrupt) 003CH ...
Page 74
Architecture Figure 8 displays the interrupt controller block diagram. Port Interrupts Internal Interrupts Figure 8. Interrupt Controller Block Diagram Operation This section describes the operational aspects of the following functions. Master Interrupt Interrupt Vectors and Interrupt Assertion: see page 58 ...
Page 75
... Interrupt Request Register likewise clears the interrupt request. Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request reg- isters. All incoming interrupts received between execution of the first the final LDX command are lost. See Example 1, which follows. ...
Page 76
... CPU, the bit in the Interrupt Request Register is automatically cleared to 0. Caution: Zilog recommends not using a coding style to generate software interrupts by setting bits in the Interrupt Request registers. All incoming interrupts received between execution of the first LDX command and the final LDX command are lost. See Example 3, which fol- lows ...
Page 77
... Caution: To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter- rupt service routine, Zilog recommends that the service routine continues to read from the RSTSTAT Register until the WDT bit is cleared as shown in the following example. CLEARWDT: LDX r0, RSTSTAT ; read reset status register to clear wdt bit ...
Page 78
Bit Description (Continued) [4] UART 0 Receiver Interrupt Request U0RXI interrupt request is pending for the UART 0 receiver. interrupt request from the UART 0 receiver is awaiting service. [3] UART 0 Transmitter Interrupt ...
Page 79
Interrupt Request 2 Register The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for both vectored and polled interrupts. When a request is presented to the interrupt controller, the corresponding bit in the IRQ2 Register becomes ...
Page 80
Table 39. IRQ0 Enable High Bit Register (IRQ0ENH) Bit 7 6 Field Reserved T1ENH RESET 0 0 R/W R/W R/W Address Bit Description [7] Reserved This bit is reserved and must be programmed to 0. [6] Timer 1 Interrupt Request ...
Page 81
Bit Description (Continued) [4] UART 0 Receive Interrupt Request Enable Low Bit U0RENL [3] UART 0 Transmit Interrupt Request Enable Low Bit U0TENL [2:1] Reserved These bits are reserved and must be programmed to 00. [0] ADC Interrupt Request Enable ...
Page 82
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH) Bit 7 6 Field PA7VENH PA6CENH PA5ENH RESET 0 0 R/W R/W R/W Address Bit Description [7] Port A Bit[7] or LVD Interrupt Request Enable High Bit PA7VENH [6] Port A Bit[7] ...
Page 83
Table 44. IRQ2 Enable and Priority Encoding IRQ2ENH[ Note: x indicates register bits 0–7. Table 45. IRQ2 Enable High Bit Register (IRQ2ENH) Bit 7 6 Field Reserved RESET 0 0 R/W R/W R/W Address Bit Description ...
Page 84
Table 46. IRQ2 Enable Low Bit Register (IRQ2ENL) Bit 7 6 Field Reserved RESET 0 0 R/W R/W R/W Address Bit Description [7:4] Reserved These bits are reserved and must be programmed to 0000. [3] Port C3 Interrupt Request Enable ...
Page 85
Shared Interrupt Select Register The Shared Interrupt Select (IRQSS) Register, shown in Table 48, determines the source of the PADxS interrupts. The Shared Interrupt Select Register selects between Port A and alternate sources for the individual interrupts. Because these shared ...
Page 86
Interrupt Control Register The Interrupt Control (IRQCTL) Register, shown in Table 49, contains the master enable bit for all interrupts. Table 49. Interrupt Control Register (IRQCTL) Bit 7 6 Field IRQE RESET 0 0 R/W R/W R Address Bit Description ...
Page 87
Timers These Z8 Encore! XP F082A Series products contain two 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (PWM) sig- nals. The timers’ feature include: • 16-bit reload counter • Programmable prescaler ...
Page 88
Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the Timer Reload High and Low Byte registers and setting the prescale ...
Page 89
Timer Output make a state change at a One-Shot time-out (rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to the start value before enabling ONE-SHOT Mode. ...
Page 90
Set the prescale value If using the Timer Output alternate function, set the initial output level (High or – Low) 2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H). This ...
Page 91
Timer Output pin changes state (from Low to High or from High to Low) at timer Reload. Observe the following steps for configuring a timer for COUNTER Mode and initiating the count: 1. Write to the Timer Control ...
Page 92
Caution: The frequency of the comparator output signal must not exceed one-fourth the system clock frequency. Further, the high or low state of the comparator output signal pulse must be no less than twice the system clock period. A shorter ...
Page 93
PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT Mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM match ...
Page 94
The PWM period is represented by the following equation: PWM Period ( initial starting value other than registers, use the ONE-SHOT Mode equation to determine the first PWM time-out period. If TPOL is set to 0, the ratio ...
Page 95
PWM output to the assertion of its complement. Observe the following steps for configuring a timer for PWM DUAL OUTPUT Mode and initiating the PWM operation: 1. Write to the ...
Page 96
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre- sented by: PWM Output High Time Ratio (%) If TPOL is set to 1, the ratio of the PWM output ...
Page 97
Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing to the relevant interrupt registers. By default, the timer interrupt is generated for both input capture and reload events. If appropriate, configure the timer interrupt ...
Page 98
Write to the Timer Reload High and Low Byte registers to set the reload value. 4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows the soft- ware to determine if interrupts were generated by ...
Page 99
Set the initial logic level (High or Low) for the Timer Output alternate function, if appropriate 2. Write to the Timer High and Low Byte registers to set the starting count value. 3. Write to the Timer Reload High ...
Page 100
Configure the timer for GATED Mode Set the prescale value – 2. Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED Mode. After ...
Page 101
Set the Capture edge (rising or falling) for the Timer Input 2. Write to the Timer High and Low Byte registers to set the starting count value (typi- cally ). 0001H 3. Write to the Timer Reload High and ...
Page 102
The timer input can be used as a selectable counting source. It shares the same pin as the complementary timer output. When selected by the GPIO Alternate Function registers, this pin functions as a timer input in all modes except ...
Page 103
Bit Description (Continued) [6:5] Timer Interrupt Configuration TICONFIG This field configures timer interrupt definition Timer Interrupt occurs on all defined Reload, Compare and Input Events. Timer Interrupt only on defined Input Capture/Deassertion Events. Timer ...
Page 104
Bit Description (Continued) [6] Timer Input/Output Polarity TPOL Operation of this bit is a function of the current operating mode of the timer. ONE-SHOT Mode When the timer is disabled, the Timer Output signal is set to the value of ...
Page 105
Bit Description (Continued) [6] GATED Mode TPOL 0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the (cont’d) falling edge of the Timer Input Timer counts when the Timer Input ...
Page 106
Bit Description (Continued) [5:3] Prescale value PRES The timer input clock is divided by 2 reset each time the Timer is disabled. This reset ensures proper clock division each time the Timer is restarted. 000 = Divide by 1. 001 ...
Page 107
Table 52. Timer 0–1 High Byte Register (TxH) Bit 7 6 Field RESET 0 0 R/W R/W R/W Address Table 53. Timer 0–1 Low Byte Register (TxL) Bit 7 6 Field RESET 0 0 R/W R/W R/W Address Bit Description ...
Page 108
Timer Reload High and Low Byte Registers The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers, shown in Tables 54 and 55, store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload High Byte ...
Page 109
Timer 0–1 PWM High and Low Byte Registers The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers, shown in Tables 56 and 57, control Pulse-Width Modulator (PWM) operations. These registers also store the Capture values for the ...
Page 110
Watchdog Timer The Watchdog Timer (WDT) protects against corrupt or unreliable software, power faults and other system-level problems which may place the Z8 Encore! XP F082A Series devices into unsuitable operating states. The features of Watchdog Timer include: • On-chip ...
Page 111
Watchdog Timer Refresh When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers. The Watchdog Timer counts down to tion is executed by the eZ8 CPU. Execution of the WDT instruction causes the ...
Page 112
WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT) Register is set to 1. ...
Page 113
Watchdog Timer Reload registers results in a one-second time-out at room tem- perature and 3.3 V supply voltage. Time-outs other than one second may be obtained by scaling the calibration values up or down as required. Note: The ...
Page 114
Watchdog Timer Reload Upper, High and Low Byte Registers The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis- ters, shown in Tables 60 through 62, form the 24-bit reload value that is loaded into the Watchdog ...
Page 115
Table 62. Watchdog Timer Reload Low Byte Register (WDTL) Bit 7 6 Field RESET R/W Address Note: A read returns the current WDT count value; a write sets the appropriate reload value. Bit Description [7:0] WDT Reload Low WDTL Least ...
Page 116
Universal Asynchronous Receiver/ Transmitter The universal asynchronous receiver/transmitter (UART full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include: • 8-bit asynchronous data ...
Page 117
Parity Checker RXD Receive Shifter Receive Data Register System Bus Transmit Data Register Transmit Shift TXD Register Parity Generator CTS DE Operation The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An even or ...
Page 118
Idle State of Line lsb 1 Start Bit0 0 Figure 11. UART Asynchronous Data Format without Parity Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 12. UART Asynchronous Data Format with Parity Transmitting Data using the Polled ...
Page 119
Set or clear the CTSE bit to enable or disable control from the remote receiver using the CTS pin 6. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data Register is empty ...
Page 120
Set or clear CTSE to enable or disable control from the remote receiver using the CTS pin 8. Execute an EI instruction to enable interrupts. The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data ...
Page 121
Read data from the UART Receive Data Register. If operating in MULTIPROCES- SOR (9-bit) Mode, further actions may be required depending on the MULTIPRO- CESSOR Mode bits MPMD[1:0]. 7. Return to Step 4 Receiving Data using the Interrupt-Driven Method ...
Page 122
The UART is now configured for interrupt-driven data reception. When the UART Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Checks the UART Status 0 Register to determine the source of the interrupt - ...
Page 123
In MULTIPROCESSOR (9-bit) Mode, the Parity (9th) bit location becomes the multipro- cessor control bit. The UART Control 1 and Status 1 registers provide MULTIPROCES- SOR (9-bit) Mode control and status information automatic address matching scheme is enabled, ...
Page 124
The third scheme is enabled by setting MPMD[1:0] to address into the UART Address Compare Register. This mode is identical to the second scheme, except that there are no interrupts on address bytes. The first data byte of each frame ...
Page 125
UART Interrupts The UART features separate interrupts for the transmitter and the receiver. In addition, when the UART primary functionality is disabled, the Baud Rate Generator can also func- tion as a basic timer with interrupt capability. Transmitter Interrupts The ...
Page 126
Receive Data Register must be read again to clear the error bits is the UART Status 0 Register. Updates to the Receive Data Register occur only when the next data word is received. UART ...
Page 127
Rate Generator to function as an additional counter if the UART functionality is not employed. UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans- mission. The input to the Baud ...
Page 128
Table 63. UART Control 0 Register (U0CTL0) Bit 7 6 Field TEN REN RESET 0 0 R/W R/W R/W Address Bit Description [7] Transmit Enable TEN This bit enables or disables the transmitter. The enable is also controlled by the ...
Page 129
Table 64. UART Control 1 Register (U0CTL1) Bit 7 6 Field MPMD[1] MPEN RESET 0 0 R/W R/W R/W Address Bit Description [7,5] MULTIPROCESSOR Mode MPMD[1,0] If MULTIPROCESSOR (9-bit) Mode is enabled The UART generates an interrupt request ...
Page 130
Bit Description (Continued) [2] Baud Rate Control BRGCTL This bit causes an alternate UART behavior depending on the value of the REN bit in the UART Control 0 Register. When the UART receiver is not enabled (REN=0), this bit deter- ...
Page 131
UART Status 0 Register The UART Status 0 (UxSTAT0) and Status 1(UxSTAT1) registers, shown in Tables 65 and 66, identify the current UART operating configuration and status. Table 65. UART Status 0 Register (U0STAT0) Bit 7 6 Field RDA PE ...
Page 132
Bit Description (Continued) [2] TDRE—Transmitter Data Register Empty TDRE This bit indicates that the UART Transmit Data Register is empty and ready for additional data. Writing to the UART Transmit Data Register resets this bit not write ...
Page 133
Table 67. UART Transmit Data Register (U0TXD) Bit 7 6 Field RESET Address Note Undefined. Bit Description [7:0] Transmit Data TXD UART transmitter data byte to be shifted out through the TXDx pin. ...
Page 134
Table 69. UART Address Compare Register (U0ADDR) Bit 7 6 Field RESET 0 0 R/W R/W R/W Address Bit Description [7:0] Compare Address COMP_ADDR This 8-bit value is compared to incoming address bytes. UART Baud Rate High and Low Byte ...
Page 135
The UART data rate is calculated using the following equation: UART Baud Rate (bits/s) For a given UART data rate, calculate the integer baud rate divisor value using the follow- ing equation: UART Baud Rate Divisor Value (BRG) The baud ...
Page 136
Table 72. UART Baud Rates (Continued) Acceptable BRG Divisor Actual Rate Rate (kHz) (Decimal) 1250.0 N/A 625.0 N/A 250.0 1 223.72 115.2 2 57.6 4 38.4 6 19.2 12 9.60 23 4.80 47 2.40 93 1.20 186 0.60 373 0.30 ...
Page 137
Infrared Encoder/Decoder Z8 Encore! XP F082A Series products contain a fully-functional, high-performance UART to Infrared Encoder/Decoder (endec). The infrared endec is integrated with an on- chip UART to allow easy communication between the Z8 Encore! XP MCU and IrDA Physical ...
Page 138
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115.2 kbaud. Higher baud rates are possible, but do not meet IrDA specifications. The UART must be enabled to ...
Page 139
Receiving IrDA Data Data received from the infrared transceiver using the IR_RXD signal through the RXD pin is decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is used by the infrared endec to ...
Page 140
The window remains open until the count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), giving the Endec a sampling window of minus four baud rate clocks to plus eight baud rate clocks ...
Page 141
Analog-to-Digital Converter The analog-to-digital converter (ADC) converts an analog input signal to its digital repre- sentation. The features of this sigma-delta ADC include: • 11-bit resolution in DIFFERENTIAL Mode • 10-bit resolution in SINGLE-ENDED Mode • Eight single-ended analog input ...
Page 142
Internal Voltage V REFSEL Reference Generator Ref Input 13 ADC Data 13 bit Sigma-Delta ADC Analog In - Analog In + ADC IRQ BUFFMODE Figure 19. Analog-to-Digital Converter Block Diagram Operation In both SINGLE-ENDED and DIFFERENTIAL modes, the effective ...
Page 143
The ADC registers actually return 13 bits of data, but the two LSBs are intended for com- pensation use only. When the software compensation routine is performed on the 13 bit raw ADC value, two bits of resolution are lost ...
Page 144
If the internal voltage reference must be output to a pin, set the The internal voltage reference must be enabled in this case. – Write the voltage reference level or to disable the internal reference. The contained in the ...
Page 145
Write to plus unbuffered or buffered mode. – Write the voltage reference level or to disable the internal reference. The contained in the ADC Control Register 0. 3. Write to the ADC Control Register 0 to configure the ADC ...
Page 146
... If you have precision references available, its own external calibration can be performed using any input modes. This calibration data takes into account buffer offset and nonlin- earity; therefore Zilog recommends that this calibration be performed separately for each of the ADC input modes planned for use. ...
Page 147
... ADC results to be scaled by a factor of 8/7. ADC Compensation Details High-efficiency assembly code that performs ADC compensation is available for down- load on www.zilog.com. This section offers a bit-specific description of the ADC compen- sation process used by this code. The following data bit definitions are used: 0– ...
Page 148
Compensation Steps: 1. Correct for Offset: ADC MSB – Offset MSB = #1 MSB 2. Compute the absolute value of the offset-corrected ADC value if negative; the gain correction factor is computed assuming positive numbers, with sign restoration after- ward. ...
Page 149
Round the result and discard the least significant two bytes (equivalent to dividing – 0x00 = #4 MSB 5. Determine the sign of the gain correction factor using the sign bits from offset-corrected ...
Page 150
Output Data The output format of the corrected ADC value is shown below. MSB – – The overflow bit in the corrected output indicates that the ...
Page 151
ADC Control Register 0 The ADC Control Register 0 (ADCCTL0) selects the analog input channel and initiates the analog-to-digital conversion. It also selects the voltage reference configuration. Table 73. ADC Control Register 0 (ADCCTL0) Bit 7 6 Field CEN REFSELL ...
Page 152
For the reserved values, all input switches are disabled to avoid leakage or other undesir- able operation. ADC samples taken with reserved bit settings are undefined. SINGLE-ENDED Mode: 0000 = ANA0 (transimpedance amp output when enabled) 0001 = ANA1 (transimpedance ...
Page 153
Table 74. ADC Control/Status Register 1 (ADCCTL1) Bit 7 6 Field REFSELH RESET 1 0 R/W R/W R/W Address Bit Description [7] Voltage Reference Level Select High Bit REFSELH In conjunction with the Low bit (REFSELL) in ADC Control Register ...
Page 154
Table 75. ADC Data High Byte Register (ADCD_H) Bit 7 6 Field RESET Address X = Undefined. Bit Description [7:0] ADC Data High Byte ADCDH This byte contains the upper eight bits of the ADC ...
Page 155
Bit Description (Continued) [2:1] Reserved These bits are reserved and must be undefined. [0] Overflow Status OVF hardware overflow did not occur in the ADC for the current sample hardware overflow did occur in the ...
Page 156
Low Power Operational Amplifier The LPO is a general-purpose low power operational amplifier. Each of the three ports of the amplifier is accessible from the package pins. The LPO contains only one pin configu- ration: ANA0 is the output/feedback node, ...
Page 157
... The comparator may be powered down to reduce supply current. See the Register 0 section on page 33 for details. Caution: Because of the propagation delay of the comparator, Zilog does not recommend enabling or reconfiguring the comparator without first disabling the interrupts and waiting for the comparator output to settle. Doing so can result in spurious interrupts. PS022827-1212 ...
Page 158
The following code example illustrates how to safely enable the comparator cmp0 load some new configuration nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei Comparator Control Register ...
Page 159
Bit Description (Continued) [5:2] Internal Reference Voltage Level REFLVL This reference is independent of the ADC voltage reference. Note: 8-pin devices contain two additional LSBs for increased resolution. For 20-/28-pin devices: 0000 = 0.0 V 0001 = 0.2 V 0010 ...
Page 160
Bit Description (Continued) [1:0] For 8-pin devices, the following voltages can be configured; for 20- and 28-pin devices, these bits are reserved. 000000 = 0.00 V 000001 = 0.05 V 000010 = 0.10 V 000011 = 0.15 V 000100 = ...
Page 161
... V reference. Because this sensor is an on-chip sensor, Zilog recommends that the user account for the difference between ambient and die temperature when inferring ambient temperature con- ditions ...
Page 162
In the above equation the temperature in ° the sensor output in volts. Assuming a compensated ADC measurement, the following equation defines the relation- ship between the ADC reading and the die temperature: ...
Page 163
Flash Memory The products in the Z8 Encore! XP F082A Series feature a nonvolatile Flash memory (8192 (4096 (2048 bytes (1024) with read/write/erase capa- bility. The Flash Memory can be ...
Page 164
Flash Program Memory Addresses (hex) 1FFF Sector 7 1C00 1BFF Sector 6 1800 17FF Sector 5 1400 13FF Sector 4 1000 0FFF Sector 3 0C00 0BFF Sector 2 0800 07FF Sector 1 0400 03FF Sector 0 0000 Figure 21. ...
Page 165
Figure 22 displays a basic Flash Controller flow. The following subsections provide details about the various operations displayed in Figure 22. Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No ...
Page 166
Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, you must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis- ters allow programming and erasing ...
Page 167
Table 79. Flash Code Protection Using the Flash Option Bits FWP Flash Code Protection Description 0 Programming and erasing disabled for all of Flash Program Mem- ory. In user code programming, Page Erase and Mass Erase are all disabled. ...
Page 168
... To exit programming mode and lock the Flash, write any value to the Flash Control Register, except the Mass Erase or Page Erase commands. PS022827-1212 to the Flash Control Register deselects 5EH . (UM0128), available for download on www.zilog.com, for a descrip ® Z8 Encore! XP F082A Series Product Specification ) ...
Page 169
... Flash memory. Page Erase operations are also supported when the Flash Controller is bypassed. For more information about bypassing the Flash Controller, refer to the Programming Support for Z8 Encore! MCUs Application Note able for download on www.zilog.com. PS022827-1212 Z8 Encore The Flash Page Select Register identi- ...
Page 170
Flash Controller Behavior in DEBUG Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger: • The Flash Write Protect option bit is ignored. • The Flash Sector ...
Page 171
Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state. The Write-only Flash Control Register shares its Register File address with the read-only Flash Status Register. PS022827-1212 Z8 Encore ...
Page 172
Table 80. Flash Control Register (FCTL) Bit 7 6 Field RESET Address Bit Description [7:0] Flash Command FCMD 73H = First unlock command. 8CH = Second unlock command. 95H = Page Erase command (must be ...
Page 173
Flash Page Select Register The Flash Page Select (FPS) Register shares address space with the Flash Sector Protect Register. Unless the Flash controller is unlocked and written with 5EH, writes to this address target the Flash Page Select Register. The ...
Page 174
Flash Sector Protect Register The Flash Sector Protect (FPROT) Register is shared with the Flash Page Select Register. When the Flash Control Register is written with the Flash Sector Protect Register. In all other cases, it targets the Flash Page ...
Page 175
Caution: The Flash Frequency High and Low Byte registers must be loaded with the correct value to ensure proper operation of the device. Also, Flash programming and erasure is not sup- ported for system clock frequencies below 20 kHz or ...
Page 176
Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore! XP F082A Series operation. The feature configuration data is stored in Flash program memory and loaded into holding registers during Reset. The features available ...
Page 177
... See the tion on page 17. Serialization Bits As an optional feature, Zilog is able to provide factory-programmed serialization. For seri- alized products, the individual devices are programmed with unique serial numbers. These serial numbers are binary values, four bytes in length. The numbers increase in size with each device, but gaps in the serial sequence may exist ...
Page 178
... Serialization Data section on page 173 Randomized Lot Identification Bits As an optional feature, Zilog is able to provide a factory-programmed random lot identi- fier. With this feature, all devices in a given production lot are programmed with the same random number. This random number is uniquely regenerated for each successive produc- tion lot and is not likely to be repeated ...
Page 179
Trim Bit Data Register The Trim Bid Data (TRMDR) Register contains the read or write data for access to the trim option bits (Table 87). Table 87. Trim Bit Data Register (TRMDR) Bit 7 6 Field RESET 0 0 R/W ...
Page 180
Bit Description (Continued) [5:4] Oscillator Mode Selection OSC_SEL[1: On-chip oscillator configured for use with external RC networks (<4 MHz Minimum power for use with very low frequency crystals (32 kHz to 1.0 MHz Medium ...
Page 181
Flash Program Memory Address 0001H Table 89. Flash Options Bits at Program Memory Address 0001H Bit 7 6 Field Reserved RESET U U R/W R/W R/W Address Note Unchanged by Reset. R/W = Read/Write. Bit Description [7:5] Reserved ...
Page 182
Trim Bit Address Space All available Trim bit addresses and their functions are listed in Table 90 through Table 95. Trim Bit Address 0000H Table 90. Trim Options Bits at Address 0000H Bit 7 6 Field RESET U U R/W ...
Page 183
Trim Bit Address 0002H Table 92. Trim Option Bits at 0002H (TIPO) Bit 7 6 Field RESET R/W Address Note Unchanged by Reset. R/W = Read/Write. Bit Description [7:0] Internal Precision Oscillator Trim Byte IPO_TRIM Contains trimming bits ...
Page 184
LVD_TRIM 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 to 11111 PS022827-1212 Table 94. LVD Trim Values LVD Threshold (V) Typical Description 3.60 Maximum LVD threshold 3.55 3.50 ...
Page 185
... Reserved R/W R/W R/W Information Page Memory 0024H Data: see page 169 Data: see page 171 Data: see page 172 Identifier: see page 174 ® Z8 Encore! XP F082A Series Product Specification R/W R/W R/W Zilog Calibration Data 168 ...
Page 186
... Differential Unbuffered ® Z8 Encore! XP F082A Series Product Specification R/W R/W R/W section on page 129. Reference Type Internal 2.0 V Internal 2.0 V Internal 2.0 V Internal 1.0 V Internal 1.0 V Internal 1.0 V External 2.0 V External 2.0 V External 2.0 V Internal 2.0 V Internal 2.0 V Internal 2.0 V External 2.0 V External 2.0 V External 2.0 V Internal 2.0 V Zilog Calibration Data 169 ...
Page 187
... Differential 1x Buffered ® F082A Series Product Specification 170 Reference Type Internal 2.0 V Internal 2.0 V Internal 2.0 V Internal 2.0 V Internal 1.0 V Internal 1.0 V Internal 1.0 V Internal 1.0 V Internal 1.0 V External 2.0 V External 2.0 V External 2.0 V External 2.0 V External 2.0 V Internal 2.0 V Internal 2.0 V Internal 2.0 V Internal 2.0 V Internal 2.0 V External 2.0 V External 2.0 V External 2.0 V External 2.0 V External 2.0 V Zilog Calibration Data ...
Page 188
... Information Page Memory 003A Temperature Sensor Operation TSCALL R/W R/W R/W Information Page Memory 003B Temperature Sensor Operation ® Z8 Encore! XP F082A Series Product Specification R/W R/W R/W on page 139 R/W R/W R/W section on page 144. Zilog Calibration Data 171 ...
Page 189
... Watchdog Timer calibration, user code must load WDTU with 0x00, WDTH with WDT- CALH and WDTL with WDTCALL. PS022827-1212 WDTCALH R/W R/W R/W Information Page Memory 007EH ® Z8 Encore! XP F082A Series Product Specification R/W R/W R/W Zilog Calibration Data 172 ...
Page 190
... Information Page Memory 001C-001F Usage Serial Number Byte 3 (most significant). Serial Number Byte 2. Serial Number Byte 1. Serial Number Byte 0 (least significant ® Z8 Encore! XP F082A Series Product Specification R/W R/W R R/W R/W R/W Zilog Calibration Data 173 ...
Page 191
... Randomized Lot ID Byte 21. Randomized Lot ID Byte 20. Randomized Lot ID Byte 19. Randomized Lot ID Byte 18. Randomized Lot ID Byte 17. Randomized Lot ID Byte 16. Randomized Lot ID Byte 15. Randomized Lot ID Byte 14 ® Z8 Encore! XP F082A Series Product Specification R/W R/W R/W Zilog Calibration Data 174 ...
Page 192
... Randomized Lot ID Byte 8. Randomized Lot ID Byte 7. Randomized Lot ID Byte 6. Randomized Lot ID Byte 5. Randomized Lot ID Byte 4. Randomized Lot ID Byte 3. Randomized Lot ID Byte 2. Randomized Lot ID Byte 1. Randomized Lot ID Byte 0 (least significant ® F082A Series Product Specification 175 Zilog Calibration Data ...
Page 193
... This memory can perform over 100,000 write cycles. Operation The NVDS is implemented by special purpose Zilog software stored in areas of program memory, which are not user-accessible. These special-purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maxi- mize the write/erase endurance of the Flash ...
Page 194
Byte Write To write a byte to the NVDS array, the user code must first push the address, then the data byte onto the stack. The user code issues a write routine (0x10B3). At the return from the sub-routine, the ...
Page 195
Byte Read To read a byte from the NVDS array, user code must first push the address onto the stack. User code issues a the return from the sub-routine, the read byte resides in working register R0 and the read ...
Page 196
Operation Read (16 byte array) Read (64 byte array) Read (128 byte array) Write (16 byte array) Write (64 byte array) Write (128 byte array) Illegal Read Illegal Write If NVDS read performance is critical to your software architecture, you ...
Page 197
On-Chip Debugger The Z8 Encore! XP F082A Series devices contain an integrated On-Chip Debugger (OCD) that provides advanced debugging features including: • Single pin interface • Reading and writing of the register file • Reading and writing of program and ...
Page 198
Operation This section describes the interface and modes of operation of the On-Chip Debugger. OCD Interface The on-chip debugger uses the DBG pin for communication with an external host. This one-pin interface is a bidirectional, open-drain interface that transmits and ...
Page 199
RS-232 TX RS-232 RX Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface DEBUG Mode The operating characteristics of the devices in DEBUG Mode are: • The eZ8 CPU fetch unit stops, idling the ...
Page 200
... Therefore, when sending the stop bit, the host must not actively drive the DBG pin High for more than 0.5 bit times. Zilog recom- mends that, if possible, the host drives the DBG pin using an open drain output to avoid this issue ...