Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 194

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
Field
Default
Value
Bit
[7:4]
[3]
RCPY
[2]
PF
[1]
AWE
[0]
DWE
Byte Write
Description
Reserved
These bits are reserved and must be programmed to 0000.
Recopy Subroutine Executed
A recopy subroutine was executed. These operations take significantly longer than a normal
write operation.
Power Failure Indicator
A power failure or system reset occurred during the most recent attempted write to the NVDS
array.
Address Write Error
An address byte failure occurred during the most recent attempted write to the NVDS array.
Data Write Error
A data byte failure occurred during the most recent attempted write to the NVDS array.
7
0
To write a byte to the NVDS array, the user code must first push the address, then the data
byte onto the stack. The user code issues a
write routine (0x10B3). At the return from the sub-routine, the write status byte resides in
working register R0. The bit fields of this status byte are defined in Table 106. The con-
tents of the status byte are undefined for write operations to illegal addresses. Also, user
code must pop the address and data bytes off the stack.
The write routine uses 13 bytes of stack space in addition to the two bytes of address and
data pushed by the user. Sufficient memory must be available for this stack usage.
Because of the Flash memory architecture, NVDS writes exhibit a nonuniform execution
time. In general, a write takes 251 µs (assuming a 20 MHz system clock). Every 400 to 500
writes, however, a maintenance operation is necessary. In this rare occurrence, the write
takes up to 61 ms to complete. Slower system clock speeds result in proportionally higher
execution times.
NVDS byte writes to invalid addresses (those exceeding the NVDS array size) have no
effect. Illegal write operations have a 2 µs execution time.
6
0
Reserved
Table 106. Write Status Byte
5
0
P R E L I M I N A R Y
4
0
CALL
RCPY
3
0
instruction to the address of the byte-
Z8 Encore! XP
PF
2
0
Product Specification
NVDS Code Interface
AWE
1
0
®
F082A Series
DWE
0
0
177