Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 76

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Caution:
Software Interrupt Assertion
Watchdog Timer Interrupt Assertion
Example 1.
To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt
Request 0 Register:
Example 2.
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request Register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request Register is
automatically cleared to 0.
Example 3.
To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt
Request registers:
Example 4.
The Watchdog Timer interrupt behavior is different from interrupts generated by other
sources. The Watchdog Timer continues to assert an interrupt as long as the time-out con-
dition continues. As it operates on a different (and usually slower) clock domain than the
rest of the device, the Watchdog Timer continues to assert this interrupt for many system
clocks until the counter rolls over.
Zilog recommends not using a coding style to generate software interrupts by setting bits
in the Interrupt Request registers. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost. See Example 3, which fol-
lows.
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
A poor coding style that can result in lost interrupt requests:
A good coding style that avoids lost interrupt requests:
A poor coding style that can result in lost interrupt requests:
A good coding style that avoids lost interrupt requests:
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F082A Series
Operation
59