Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 65

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7:0]
POCx
Note: x indicates the specific GPIO port pin number (7–0).
Bit
Field
RESET
R/W
Address
Bit
[7:0]
PHDEx
Note: x indicates the specific GPIO port pin number (7–0).
Description
Port Output Control
These bits function independently of the alternate function bit and always disable the drains if
set to 1.
0 = The source current is enabled for any output mode unless overridden by the alternate func-
1 = The source current for the associated pin is disabled (open-drain mode).
Description
Port High Drive Enabled
0 = The port pin is configured for standard output current drive.
1 = The port pin is configured for high output current drive.
PHDE7
POC7
R/W
R/W
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
If 04H in Port A–D Address Register, accessible through the Port A–D Control Register
tion (push-pull output).
7
7
0
Port A–D High Drive Enable Subregisters
The Port A–D High Drive Enable Subregister, shown in Table 24, is accessed through the
port A–D Control Register by writing
bits in the Port A–D High Drive Enable subregisters to 1 configures the specified port pins
for high current output drive operation. The Port A–D High Drive Enable subregister
affects the pins directly and, as a result, alternate functions are also affected.
Table 24. Port A–D High Drive Enable Subregisters (PxHDE)
Table 23. Port A–D Output Control Subregisters (PxOC)
PHDE6
POC6
R/W
R/W
6
6
0
PHDE5
POC5
R/W
R/W
5
5
0
P R E L I M I N A R Y
00H (Ports A-C); 01H (Port D)
PHDE4
POC4
R/W
R/W
4
4
0
04H
to the Port A–D Address Register. Setting the
PHDE3
POC3
R/W
R/W
3
3
0
Z8 Encore! XP
GPIO Control Register Definitions
PHDE2
POC2
R/W
R/W
2
2
0
Product Specification
PHDE1
POC1
R/W
R/W
1
1
0
®
F082A Series
PHDE0
POC0
R/W
R/W
0
0
0
48