Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 128

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7]
TEN
[6]
REN
[5]
CTSE
[4]
PEN
[3]
PSEL
[2]
SBRK
[1]
STOP
[0]
LBEN
Description
Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled. 
0 = Transmitter disabled.
1 = Transmitter enabled.
Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-
tional parity bit.
Parity Select
0 = Even parity is transmitted and expected on all received data. 
1 = Odd parity is transmitted and expected on all received data.
Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit. 
0 = No break is sent.
1 = Forces a break condition by setting the output of the transmitter to zero.
Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
TEN
R/W
7
0
REN
R/W
6
0
Table 63. UART Control 0 Register (U0CTL0)
CTSE
R/W
5
0
P R E L I M I N A R Y
PEN
R/W
4
0
F42H
PSEL
R/W
3
0
Z8 Encore! XP
UART Control Register Definitions
SBRK
R/W
2
0
Product Specification
STOP
R/W
1
0
®
F082A Series
LBEN
R/W
0
0
111

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